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* Reapplying [FastISel][AArch64] Cleanup constant materialization code. NFCI.Juergen Ributzka2014-08-151-26/+30
| | | | | | | | | | Note: This reapplies r215582 without any modifications. The refactoring wasn't responsible for the buildbot failures. Original commit message: Cleanup and prepare constant materialization code for future commits. llvm-svn: 215752
* Revert several FastISel commits to track down a buildbot error.Juergen Ributzka2014-08-141-42/+26
| | | | | | | | | | | | This reverts: r215595 "[FastISel][X86] Add large code model support for materializing floating-point constants." r215594 "[FastISel][X86] Use XOR to materialize the "0" value." r215593 "[FastISel][X86] Emit more efficient instructions for integer constant materialization." r215591 "[FastISel][AArch64] Make use of the zero register when possible." r215588 "[FastISel] Let the target decide first if it wants to materialize a constant." r215582 "[FastISel][AArch64] Cleanup constant materialization code. NFCI." llvm-svn: 215673
* Revert "[FastISel][AArch64] Add support for more addressing modes."Juergen Ributzka2014-08-141-289/+168
| | | | | | This reverts commits r215597, because it might have broken the build bots. llvm-svn: 215659
* Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly ↵Aaron Ballman2014-08-141-1/+1
| | | | | | converted to 64 bits (was 64-bit shift intended?)). NFC. llvm-svn: 215642
* AArch64: Silence warning in AArch64FastISelDavid Majnemer2014-08-141-1/+1
| | | | | | GCC was emitting a signed vs unsigned comparison warning. llvm-svn: 215620
* [AArch64, fast-isel] Fall back to SelectionDAG to select tail calls.Akira Hatanaka2014-08-131-0/+5
| | | | | | | | | | Certain functions such as objc_autoreleaseReturnValue have to be called as tail-calls even at -O0. Since normal fast-isel doesn't emit calls as tail calls, we have to fall back to SelectionDAG to select calls that are marked as tail. <rdar://problem/17991614> llvm-svn: 215600
* [FastISel][AArch64] Add support for more addressing modes.Juergen Ributzka2014-08-131-168/+289
| | | | | | | | | | | | | | | | | FastISel didn't take much advantage of the different addressing modes available to it on AArch64. This commit allows the ComputeAddress method to recognize more addressing modes that allows shifts and sign-/zero-extensions to be folded into the memory operation itself. For Example: lsl x1, x1, #3 --> ldr x0, [x0, x1, lsl #3] ldr x0, [x0, x1] sxtw x1, w1 lsl x1, x1, #3 --> ldr x0, [x0, x1, sxtw #3] ldr x0, [x0, x1] llvm-svn: 215597
* [FastISel][AArch64] Make use of the zero register when possible.Juergen Ributzka2014-08-131-1/+13
| | | | | | | | | | This change materializes now the value "0" from the zero register. The zero register can be folded by several instruction, so no materialization is need at all. Fixes <rdar://problem/17924413>. llvm-svn: 215591
* [FastISel][AArch64] Cleanup constant materialization code. NFCI.Juergen Ributzka2014-08-131-26/+30
| | | | | | Cleanup and prepare constant materialization code for future commits. llvm-svn: 215582
* [FastISel][AArch64] Attach MachineMemOperands to load and store instructions.Juergen Ributzka2014-08-081-17/+29
| | | | llvm-svn: 215231
* Remove the target machine from CCState. Previously it was only usedEric Christopher2014-08-061-4/+3
| | | | | | | | | to get the subtarget and that's accessible from the MachineFunction now. This helps clear the way for smaller changes where we getting a subtarget will require passing in a MachineFunction/Function as well. llvm-svn: 214988
* [FastIsel][AArch64] Fix previous commit r214844 (Don't perform ↵Juergen Ributzka2014-08-051-6/+4
| | | | | | | | | | | | | | sign-/zero-extension for function arguments that have already been sign-/zero-extended.) The original code would fail for unsupported value types like i1, i8, and i16. This fix changes the code to only create a sub-register copy for i64 value types and all other types (i1/i8/i16/i32) just use the source register without any modifications. getRegClassFor() is now guarded by the i64 value type check, that guarantees that we always request a register for a valid value type. llvm-svn: 214848
* [FastISel][AArch64] Implement the FastLowerArguments hook.Juergen Ributzka2014-08-051-0/+103
| | | | | | | | | | | | | This implements basic argument lowering for AArch64 in FastISel. It only handles a small subset of the C calling convention. It supports simple arguments that can be passed in GPR and FPR registers. This should cover most of the trivial cases without falling back to SelectionDAG. This fixes <rdar://problem/17890986>. llvm-svn: 214846
* [FastISel][AArch64] Don't perform sign-/zero-extension for function ↵Juergen Ributzka2014-08-051-2/+24
| | | | | | arguments that have already been sign-/zero-extended. llvm-svn: 214844
* [FastISel][AArch64] Fix shift lowering for i8 and i16 value types.Juergen Ributzka2014-08-041-15/+13
| | | | | | | | | | | | | | | This fix changes the parameters #r and #s that are passed to the UBFM/SBFM instruction to get the zero/sign-extension for free. The original problem was that the shift left would use the 32-bit shift even for i8/i16 value types, which could leave the upper bits set with "garbage" values. The arithmetic shift right on the other side would use the wrong MSB as sign-bit to determine what bits to shift into the value. This fixes <rdar://problem/17907720>. llvm-svn: 214788
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-1/+2
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [FastISel][AArch64] Fold offset into the memory operation.Juergen Ributzka2014-08-011-0/+7
| | | | | | | | | | | | Fold simple offsets into the memory operation: add x0, x0, #8 ldr x0, [x0] --> ldr x0, [x0, #8] Fixes <rdar://problem/17887945>. llvm-svn: 214545
* [FastISel][AArch64] Add branch weights.Juergen Ributzka2014-08-011-5/+38
| | | | | | | | | Add branch weights to branch instructions, so that the following passes can optimize based on it (i.e. basic block ordering). Fixes <rdar://problem/17887137>. llvm-svn: 214537
* [FastISel][AArch64] Fix the immediate versions of the ↵Juergen Ributzka2014-08-011-48/+49
| | | | | | | | | | | | {s|u}{add|sub}.with.overflow intrinsics. ADDS and SUBS cannot encode negative immediates or immediates larger than 12bit. This fix checks if the immediate version can be used under this constraints and if we can convert ADDS to SUBS or vice versa to support negative immediates. Also update the test cases to test the immediate versions. llvm-svn: 214470
* [FastISel][AArch64] Add basic bitcast support for conversion between float ↵Juergen Ributzka2014-07-311-0/+37
| | | | | | | | and int. Fixes <rdar://problem/17867078>. llvm-svn: 214389
* [FastISel][AArch64] Add sqrt intrinsic support.Juergen Ributzka2014-07-311-0/+19
| | | | | | Fixes <rdar://problem/17867067>. llvm-svn: 214388
* [FastISel][AArch64] Add MachO large code model support for function calls.Juergen Ributzka2014-07-311-10/+105
| | | | | | | | | Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
* [FastISel][AArch64 and X86] Don't emit stores for UNDEF arguments during ↵Juergen Ributzka2014-07-311-0/+4
| | | | | | | | | | function call lowering. UNDEF arguments are not ment to be touched - especially for the webkit_js calling convention. This fix reproduces the already existing behavior of SelectionDAG in FastISel. llvm-svn: 214366
* [FastISel][AArch64] Add select folding support for the XALU intrinsics.Juergen Ributzka2014-07-301-34/+36
| | | | | | | | | | | This improves the code generation for the XALU intrinsics when the condition is feeding a select instruction. This also updates and enables the XALU unit tests for FastISel. This fixes <rdar://problem/17831117>. llvm-svn: 214350
* [FastISel][AArch64] Add branch folding support for the XALU intrinsics.Juergen Ributzka2014-07-301-3/+77
| | | | | | | | | This improves the code generation for the XALU intrinsics when the condition is feeding a branch instruction. This is related to <rdar://problem/17831117>. llvm-svn: 214349
* [FastISel][AArch64] Add {s|u}{add|sub|mul}.with.overflow intrinsic support.Juergen Ributzka2014-07-301-0/+171
| | | | | | | | | | This commit adds support for the {s|u}{add|sub|mul}.with.overflow intrinsics. The unit tests for FastISel will be enabled in a later commit, once there is also branch and select folding support. This is related to <rdar://problem/17831117>. llvm-svn: 214348
* [FastISel][AArch64] Create helper functions to create the various multiplies ↵Juergen Ributzka2014-07-301-24/+70
| | | | | | on AArch64. llvm-svn: 214346
* [FastISel][AArch64] Add support for shift-immediate.Juergen Ributzka2014-07-301-1/+101
| | | | | | | | Currently the shift-immediate versions are not supported by tblgen and hopefully this can be later removed, once the required support has been added to tblgen. llvm-svn: 214345
* [FastISel][AArch64] Add support for frameaddress intrinsic.Juergen Ributzka2014-07-251-2/+28
| | | | | | | | | | | | This commit implements the frameaddress intrinsic for the AArch64 architecture in FastISel. There were two test cases that pretty much tested the same, so I combined them to a single test case. Fixes <rdar://problem/17811834> llvm-svn: 213959
* Run sort_includes.py on the AArch64 backend.Benjamin Kramer2014-07-251-1/+1
| | | | | | No functionality change. llvm-svn: 213938
* [FastISel][AArch64] Fix return type in FastLowerCall.Juergen Ributzka2014-07-231-4/+4
| | | | | | | | | | I used the wrong method to obtain the return type inside FinishCall. This fix simply uses the return type from FastLowerCall, which we already determined to be a valid type. Reduced test case from Chad. Thanks. llvm-svn: 213788
* [FastIsel][AArch64] Add support for the FastLowerCall and ↵Juergen Ributzka2014-07-221-136/+81
| | | | | | | | | | | | | FastLowerIntrinsicCall target-hooks. This commit modifies the existing call lowering functions to be used as the FastLowerCall and FastLowerIntrinsicCall target-hooks instead. This enables patchpoint intrinsic lowering for AArch64. This fixes <rdar://problem/17733076> llvm-svn: 213704
* AArch64: correctly fast-isel i8 & i16 multipliesTim Northover2014-07-101-0/+1
| | | | | | | | We were asking for a register for type i8 or i16 which caused an assert. rdar://problem/17620015 llvm-svn: 212718
* Make AArch64FastISel::EmitIntExt explicitly check its source and destination ↵Louis Gerbarg2014-07-091-3/+8
| | | | | | | | | | | | types This is a follow up to r212492. There should be no functional difference, but this patch makes it clear that SrcVT must be an i1/i8/16/i32 and DestVT must be an i8/i16/i32/i64. rdar://17516686 llvm-svn: 212633
* Allow AArch64FastISel to degrade graceully in the presence of an MVT::i128Louis Gerbarg2014-07-071-0/+6
| | | | | | | | | | | | | | | | | Currently AArch64FastISel crashes if it tries to extend an integer into an MVT::i128. This can happen by creating 128 bit integers like so: typedef unsigned int uint128_t __attribute__((mode(TI))); typedef int sint128_t __attribute__((mode(TI))); This patch makes EmitIntExt check for their presence and then falls back to SelectionDAG. Tests included. rdar://17516686 llvm-svn: 212492
* AArch64: teach FastISel how to handle offset FrameIndicesTim Northover2014-06-101-4/+11
| | | | | | | | | | Previously we were abandonning the attempt, leading to some combination of extra work (when selection of a load/store fails completely) and inferior code (when this leads to a real memcpy call instead of inlining). rdar://problem/17187463 llvm-svn: 210520
* AArch64: make FastISel memcpy emission more robust.Tim Northover2014-06-101-3/+5
| | | | | | | | | | We were hitting an assert if FastISel couldn't create the load or store we requested. Currently this happens for large frame-local addresses, though CodeGen could be improved there. rdar://problem/17187463 llvm-svn: 210519
* AArch64: mark small types (i1, i8, i16) as promotedTim Northover2014-06-031-3/+1
| | | | | | | | | This means the output of LowerFormalArguments returns a lowered SDValue with the correct type (expected in SelectionDAGBuilder). Without this, an assertion under a DEBUG macro triggers when those types are passed on the stack. llvm-svn: 210102
* [pr19844] Add thread local mode to aliases.Rafael Espindola2014-05-281-9/+3
| | | | | | | | | | This matches gcc's behavior. It also seems natural given that aliases contain other properties that govern how it is accessed (linkage, visibility, dll storage). Clang still has to be updated to expose this feature to C. llvm-svn: 209759
* AArch64: simplify calling conventions slightly.Tim Northover2014-05-261-1/+0
| | | | | | | | | We can eliminate the custom C++ code in favour of some TableGen to check the same things. Functionality should be identical, except for a buffer overrun that was present in the C++ code and meant webkit failed if any small argument needed to be passed on the stack. llvm-svn: 209636
* AArch64: disable FastISel for large code model.Tim Northover2014-05-241-0/+5
| | | | | | | | | The code emitted is what would be expected for the small model, so it shouldn't be used when objects can be the full 64-bits away. This fixes MCJIT tests on Linux. llvm-svn: 209585
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+1977
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
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