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* [MIPS][ELF] Use PC-relative relocations in .eh_frame when possibleAlex Richardson2020-01-131-0/+3
| | | | | | | | | | | | | | | | | | | | When compiling position-independent executables, we now use DW_EH_PE_pcrel | DW_EH_PE_sdata4. However, the MIPS ABI does not define a 64-bit PC-relative ELF relocation so we cannot use sdata8 for the large code model case. When using the large code model, we fall back to the previous behaviour of generating absolute relocations. With this change clang-generated .o files can be linked by LLD without having to pass -Wl,-z,notext (which creates text relocations). This is simpler than the approach used by ld.bfd, which rewrites the .eh_frame section to convert absolute relocations into relative references. I saw in D13104 that apparently ld.bfd did not accept pc-relative relocations for MIPS ouput at some point. However, I also checked that recent ld.bfd can process the clang-generated .o files so this no longer seems true. Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D72228
* [Object][RISCV] Resolve R_RISCV_32_PCRELLuís Marques2019-11-211-0/+3
| | | | | | | | | | | | | Summary: Add support for resolving `R_RISCV_32_PCREL` relocations. Those aren't actually resolved AFAIK, but support is still needed to avoid llvm-dwarfdump errors. The use of these relocations was introduced in D66419 but the corresponding resolving wasn't added then. The test adds a check that should catch future unresolved relocations. Reviewers: asb, lenary Reviewed By: asb Tags: #llvm Differential Revision: https://reviews.llvm.org/D70204
* [Object][RISCV] Fix R_RISCV_SET6 and R_RISCV_SUB6 relocations resolutionLuís Marques2019-11-211-2/+2
| | | | | | | | | | Summary: These relocations had a suspicious resolution logic, given their name. This patch makes the resolution match the LLD one, which makes more sense. Reviewers: asb, lenary, HsiangKai, jrtc27 Reviewed By: HsiangKai Tags: #llvm Differential Revision: https://reviews.llvm.org/D70396
* Support for 64-bit PC-relative relocations for X86_64Artur Pilipenko2019-09-211-0/+2
| | | | | | | | | | | | | | | | | | | | | ELF files generated for X86_64 targets may contain 64-bit PC-relative relocations. For instance, an exception handler table entry contains the start of exception-throwing frame relative to the start of exception handler. As these two labels belong to different sections, their difference and so the relocation is 64-bit. An attempt to parse such file, i.e. in DWARFContext::create, results in "failed to compute relocation" error. This fix adds support for such relocations to RelocationResolver.cpp. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D67779 Patch by Oleg Pliss (Oleg.Pliss@azul.com) llvm-svn: 372447
* [Object] Implement relocation resolver for COFF ARM/ARM64Martin Storsjo2019-09-101-2/+53
| | | | | | | | | | Adding testscases for this via llvm-dwarfdump. Also add testcases for the existing resolver support for X86. Differential Revision: https://reviews.llvm.org/D67340 llvm-svn: 371515
* [BPF] Fix bpf llvm-objdump issues.Yonghong Song2019-08-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit https://reviews.llvm.org/D57939 ("[DWARF] Refactor RelocVisitor and fix computation of SHT_RELA-typed relocation entries) made a change for relocation resolution when operating on an object file. The change unfortunately broke BPF as given SymbolValue (S) and Addent (A), previously relocation is resolved to S + A and after the change, it is resolved to S This patch fixed the issue by resolving relocation correctly. It looks not all relocation resolution reaches here and I did not trace down exactly when. But I do find if the object file includes codes in two different ELF sections than default ".text", the above bug will be triggered. This patch included a trivial two function source code to demonstrate this issue. The relocation for .debug_loc is resolved incorrectly due to this and llvm-objdump cannot display source annotated assembly. Differential Revision: https://reviews.llvm.org/D66372 llvm-svn: 369199
* [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.Hsiangkai Wang2019-07-191-0/+6
| | | | | | | | | | | | | It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366524
* Revert "[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame."Hsiangkai Wang2019-07-181-6/+0
| | | | | | This reverts commit 17e3cbf5fe656483d9016d0ba9e1d0cd8629379e. llvm-svn: 366444
* [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.Hsiangkai Wang2019-07-181-0/+6
| | | | | | | | | | | | | It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366442
* [DWARF][RISCV] Add support for RISC-V relocations needed for debug infoAlex Bradbury2019-07-181-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When code relaxation is enabled many RISC-V fixups are not resolved but instead relocations are emitted. This happens even for DWARF debug sections. Therefore, to properly support the parsing of DWARF debug info we need to be able to resolve RISC-V relocations. This patch adds: * Support for RISC-V relocations in RelocationResolver * DWARF support for two relocations per object file offset * DWARF changes to support relocations in more DIE fields The two relocations per offset change is needed because some RISC-V relocations (used for label differences) come in pairs. Relocations can also be emitted for DWARF fields where relocations were not yet evaluated. Adding relocation support for some of these fields is essencial. On the other hand, LLVM currently emits RISC-V relocations for fixups that could be safely evaluated, since they can never be affected by code relaxations. This patch also adds relocation support for the fields affected by those extraneous relocations (the DWARF unit entry Length, and the DWARF debug line entry TotalLength and PrologueLength), for testing purposes. Differential Revision: https://reviews.llvm.org/D62062 Patch by Luís Marques. llvm-svn: 366402
* [DWARF] Refactor RelocVisitor and fix computation of SHT_RELA-typed ↵Fangrui Song2019-03-221-0/+497
relocation entries Summary: getRelocatedValue may compute incorrect value for SHT_RELA-typed relocation entries. // DWARFDataExtractor.cpp uint64_t DWARFDataExtractor::getRelocatedValue(uint32_t Size, uint32_t *Off, ... // This formula is correct for REL, but may be incorrect for RELA if the value // stored in the location (getUnsigned(Off, Size)) is not zero. return getUnsigned(Off, Size) + Rel->Value; In this patch, we * refactor these visit* functions to include a new parameter `uint64_t A`. Since these visit* functions are no longer used as visitors, rename them to resolve*. + REL: A is used as the addend. A is the value stored in the location where the relocation applies: getUnsigned(Off, Size) + RELA: The addend encoded in RelocationRef is used, e.g. getELFAddend(R) * and add another set of supports* functions to check if a given relocation type is handled. DWARFObjInMemory uses them to fail early. Reviewers: echristo, dblaikie Reviewed By: echristo Subscribers: mgorny, aprantl, aheejin, fedor.sergeev, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57939 llvm-svn: 356729
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