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| author | Hsiangkai Wang <hsiangkai@gmail.com> | 2019-07-19 02:03:34 +0000 |
|---|---|---|
| committer | Hsiangkai Wang <hsiangkai@gmail.com> | 2019-07-19 02:03:34 +0000 |
| commit | 18ccfadd4630878275f1142de7bd1b4e55ee2989 (patch) | |
| tree | f7dc54ad9e05a3aa51682d1ac164be0af01081cf /llvm/lib/Object/RelocationResolver.cpp | |
| parent | ccbffefccaff42b0d094c9ef0f49fc3e8c8456ea (diff) | |
| download | bcm5719-llvm-18ccfadd4630878275f1142de7bd1b4e55ee2989.tar.gz bcm5719-llvm-18ccfadd4630878275f1142de7bd1b4e55ee2989.zip | |
[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.
It is necessary to generate fixups in .debug_frame or .eh_frame as
relaxation is enabled due to the address delta may be changed after
relaxation.
There is an opcode with 6-bits data in debug frame encoding. So, we
also need 6-bits fixup types.
Differential Revision: https://reviews.llvm.org/D58335
llvm-svn: 366524
Diffstat (limited to 'llvm/lib/Object/RelocationResolver.cpp')
| -rw-r--r-- | llvm/lib/Object/RelocationResolver.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Object/RelocationResolver.cpp b/llvm/lib/Object/RelocationResolver.cpp index 0a243f32e12..8738e2e9f3b 100644 --- a/llvm/lib/Object/RelocationResolver.cpp +++ b/llvm/lib/Object/RelocationResolver.cpp @@ -335,6 +335,8 @@ static bool supportsRISCV(uint64_t Type) { case ELF::R_RISCV_NONE: case ELF::R_RISCV_32: case ELF::R_RISCV_64: + case ELF::R_RISCV_SET6: + case ELF::R_RISCV_SUB6: case ELF::R_RISCV_ADD8: case ELF::R_RISCV_SUB8: case ELF::R_RISCV_ADD16: @@ -358,6 +360,10 @@ static uint64_t resolveRISCV(RelocationRef R, uint64_t S, uint64_t A) { return (S + RA) & 0xFFFFFFFF; case ELF::R_RISCV_64: return S + RA; + case ELF::R_RISCV_SET6: + return (A + (S + RA)) & 0xFF; + case ELF::R_RISCV_SUB6: + return (A - (S + RA)) & 0xFF; case ELF::R_RISCV_ADD8: return (A + (S + RA)) & 0xFF; case ELF::R_RISCV_SUB8: |
