summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* Fix PR3391 and PR3864. Reg allocator infinite looping.Evan Cheng2009-03-232-6/+14
| | | | llvm-svn: 67544
* Don't set SUnit::hasPhysRegDefs to true unless the defs areDan Gohman2009-03-231-1/+4
| | | | | | actually have uses, which reflects the way it's used. llvm-svn: 67540
* Fix canClobberPhysRegDefs to check all SDNodes grouped togetherDan Gohman2009-03-231-14/+19
| | | | | | | in an SUnit, instead of just the first one. This fix is needed by some upcoming scheduler changes. llvm-svn: 67531
* Add a new bit to SUnit to record whether a node has implicit physregDan Gohman2009-03-231-3/+6
| | | | | | defs, regardless of whether they are actually used. llvm-svn: 67528
* Now that errs() is properly non-buffered, there's no need toDan Gohman2009-03-233-4/+2
| | | | | | explicitly flush it. llvm-svn: 67526
* Model inline asm constraint which ties an input to an output register as ↵Evan Cheng2009-03-234-38/+92
| | | | | | machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. llvm-svn: 67512
* Do not fold away subreg_to_reg if the source register has a sub-register ↵Evan Cheng2009-03-231-3/+9
| | | | | | | | | | index. That means the source register is taking a sub-register of a larger register. e.g. On x86 %RAX<def> = ... %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3 The first def is defining RAX, not EAX so the top bits were not zero-extended. llvm-svn: 67511
* Simplify this code; use a while instead of an if and a do-while.Dan Gohman2009-03-201-9/+6
| | | | llvm-svn: 67400
* For inline asm output operand that matches an input. Encode the input ↵Evan Cheng2009-03-206-29/+44
| | | | | | operand index in the high bits. llvm-svn: 67387
* Fixed build warnings for unused variables.Sanjiv Gupta2009-03-201-3/+0
| | | | llvm-svn: 67372
* Fixed the comment. No functionality change.Sanjiv Gupta2009-03-201-4/+4
| | | | llvm-svn: 67370
* Apply the patch requested in PR3846.Chris Lattner2009-03-201-1/+1
| | | | llvm-svn: 67364
* Fix the Win32 VS2008 build:Sebastian Redl2009-03-191-1/+1
| | | | | | | | | | - Make type declarations match the struct/class keyword of the definition. - Move AddSignalHandler into the namespace where it belongs. - Correctly call functions from template base. - Some other small changes. With this patch, LLVM and Clang should build properly and with far less noise under VS2008. llvm-svn: 67347
* Added MachineInstr::isRegTiedToDefOperand to check for two-addressness.Evan Cheng2009-03-195-24/+37
| | | | llvm-svn: 67335
* Fix PEI to not walk off the start of a block when an updated instructionChris Lattner2009-03-191-2/+6
| | | | | | is the first in its block. This is PR3842. llvm-svn: 67304
* Added missing support for widening when splitting an unary op (PR3683)Mon P Wang2009-03-184-4/+91
| | | | | | | and expanding a bit convert (PR3711). In both cases, we extract the valid part of the widen vector and then do the conversion. llvm-svn: 67175
* Don't force promotion of return arguments on the callee.Rafael Espindola2009-03-171-9/+0
| | | | | | | Some architectures (like x86) don't require it. This fixes bug 3779. llvm-svn: 67132
* Fix codegen to compute the size of an allocation by multiplying theChris Lattner2009-03-171-8/+17
| | | | | | | | | | | size by the array amount as an i32 value instead of promoting from i32 to i64 then doing the multiply. Not doing this broke wrap-around assumptions that the optimizers (validly) made. The ultimate real fix for this is to introduce i64 version of alloca and remove mallocinst. This fixes PR3829 llvm-svn: 67093
* r66870 missed this out.Sanjiv Gupta2009-03-171-0/+1
| | | | llvm-svn: 67082
* Reapply r67049, with the test adjusted for darwinDuncan Sands2009-03-171-39/+61
| | | | | | (which produces "call L_f$stub" rather than "call f"). llvm-svn: 67079
* Fix a problem with DAGCombine where we were building an illegal buildMon P Wang2009-03-171-6/+11
| | | | | | | | vector shuffle mask. Forced the mask to be built using i32. Note: this will be irrelevant once vector_shuffle no longer takes a build vector for the shuffle mask. llvm-svn: 67076
* Spiller may unfold load / mod / store instructions as an optimization when ↵Evan Cheng2009-03-172-9/+30
| | | | | | the would be loaded value is available in a register. It needs to check if it's legal to clobber the register. Also, the register can contain values of multiple spill slots, make sure to check all instead of just the one being unfolded. llvm-svn: 67068
* --- Reverse-merging (from foreign repository) r67049 into '.':Bill Wendling2009-03-161-61/+39
| | | | | | | | | | | | | | | | U test/CodeGen/X86/2009-03-13-PHIElimBug.ll D test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll U lib/CodeGen/PHIElimination.cpp r67049 was causing this failure: Running /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/X86/dg.exp ... FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/X86/2009-03-13-PHIElimBug.ll for PR3784 Failed with exit(1) at line 1 while running: llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/X86/2009-03-13-PHIElimBug.ll | llc -march=x86 | /usr/bin/grep -A 2 {call f} | /usr/bin/grep movl child process exited abnormally llvm-svn: 67051
* Tweak the fix for PR3784: be less sensitive about justDuncan Sands2009-03-161-39/+61
| | | | | | | | | | | | | | | | | | how invokes are set up. The fix could be disturbed by register copies coming after the EH_LABEL, and also didn't behave quite right when it was the invoke result that was used in a phi node. Also (see new testcase) fix another phi elimination bug while there: register copies in the landing pad need to come after the EH_LABEL, because that's where execution branches to when unwinding. If they come before the EH_LABEL then they will never be executed... Also tweak the original testcase so it doesn't use a no-longer existing counter. The accumulated phi elimination changes fix two of seven Ada testsuite failures that turned up after landing pad critical edge splitting was turned off. So there's probably more to come. llvm-svn: 67049
* Give the pre-alloc splitter access to the VirtRegMap. It doesn't do anythingOwen Anderson2009-03-141-0/+8
| | | | | | useful with it at the moment, but it will in the future. llvm-svn: 67012
* Add newlines at end of file (this can annoy gcov)Daniel Dunbar2009-03-142-2/+2
| | | | llvm-svn: 67000
* Avoid doing the transformation c ? 1.0 : 2.0 as load { 2.0, 1.0 } + c*4Mon P Wang2009-03-141-1/+4
| | | | | | | if FPConstant is legal because if the FPConstant doesn't need to be stored in a constant pool, the transformation is unlikely to be profitable. llvm-svn: 66994
* Improve FastISel's handling of truncates to i1, and implementDan Gohman2009-03-131-10/+18
| | | | | | | | ptrtoint and inttoptr in X86FastISel. These casts aren't always handled in the generic FastISel code because X86 sometimes needs custom code to do truncation and zero-extension. llvm-svn: 66988
* Fix PR3784: If the source of a phi comes from a bb ended with an invoke, ↵Evan Cheng2009-03-131-0/+40
| | | | | | | | make sure the copy is inserted before the try range (unless it's used as an input to the invoke, then insert it after the last use), not at the end of the bb. Also re-apply r66140 which was disabled as a workaround. llvm-svn: 66976
* Fix FastISel's assumption that i1 values are always zero-extendedDan Gohman2009-03-131-1/+14
| | | | | | | | | by inserting explicit zero extensions where necessary. Included is a testcase where SelectionDAG produces a virtual register holding an i1 value which FastISel previously mistakenly assumed to be zero-extended. llvm-svn: 66941
* Fix some significant problems with constant pools that resulted in ↵Evan Cheng2009-03-138-67/+69
| | | | | | | | | | | | | | | | | | | | | | | unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. llvm-svn: 66875
* Convert VirtRegMap to a MachineFunctionPass.Owen Anderson2009-03-134-28/+63
| | | | llvm-svn: 66870
* Oops...I committed too much.Bill Wendling2009-03-136-46/+65
| | | | llvm-svn: 66867
* Temporarily XFAIL this test.Bill Wendling2009-03-136-65/+46
| | | | llvm-svn: 66866
* Fix a typo in a comment.Dan Gohman2009-03-121-1/+1
| | | | llvm-svn: 66843
* Reorganize some #include's.Owen Anderson2009-03-122-5/+4
| | | | llvm-svn: 66780
* Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"Chris Lattner2009-03-121-76/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | related transformations out of target-specific dag combine into the ARM backend. These were added by Evan in r37685 with no testcases and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll). Add some simple X86-specific (for now) DAG combines that turn things like cond ? 8 : 0 -> (zext(cond) << 3). This happens frequently with the recently added cp constant select optimization, but is a very general xform. For example, we now compile the second example in const-select.ll to: _test: movsd LCPI2_0, %xmm0 ucomisd 8(%esp), %xmm0 seta %al movzbl %al, %eax movl 4(%esp), %ecx movsbl (%ecx,%eax,4), %eax ret instead of: _test: movl 4(%esp), %eax leal 4(%eax), %ecx movsd LCPI2_0, %xmm0 ucomisd 8(%esp), %xmm0 cmovbe %eax, %ecx movsbl (%ecx), %eax ret This passes multisource and dejagnu. llvm-svn: 66779
* Enable Chris' value propagation change. It make available known sign, zero, ↵Evan Cheng2009-03-121-3/+1
| | | | | | one bits information for values that are live out of basic blocks. The goal is to eliminate unnecessary sext, zext, truncate of values that are live-in to blocks. This does not handle PHI nodes yet. llvm-svn: 66777
* updateGabor Greif2009-03-111-0/+1
| | | | llvm-svn: 66733
* Reorganization: Move the Spiller out of VirtRegMap.cpp into its own files. ↵Owen Anderson2009-03-116-1886/+1971
| | | | | | No (intended) functionality change. llvm-svn: 66720
* My last coalescer fix introduced a subtler one. It's aborting a commuting ↵Evan Cheng2009-03-111-5/+11
| | | | | | optimization too late and left the live intervals to be out of sync with instructions. This fixes 8b10b. llvm-svn: 66715
* It makes no sense to have a ODR version of commonDuncan Sands2009-03-111-2/+1
| | | | | | linkage, so remove it. llvm-svn: 66690
* Add parentheses to pacify gcc-4.3.Duncan Sands2009-03-111-1/+1
| | | | llvm-svn: 66653
* reapply my previous patch (r66358) with a tweak to set theChris Lattner2009-03-111-2/+55
| | | | | | | | | alignment of the generated constant pool entry to the desired alignment of a type. If we don't do this, we end up trying to do movsd from 4-byte alignment memory. This fixes 450.soplex and 456.hmmer. llvm-svn: 66641
* Put the assignment back at the top of this method.Bill Wendling2009-03-111-2/+2
| | | | llvm-svn: 66611
* Two coalescer fixes in one.Evan Cheng2009-03-112-8/+61
| | | | | | | 1. Use the same value# to represent unknown values being merged into sub-registers. 2. When coalescer commute an instruction and the destination is a physical register, update its sub-registers by merging in the extended ranges. llvm-svn: 66610
* Make ivars private. Other cleanup. No functionality change.Bill Wendling2009-03-101-59/+27
| | | | llvm-svn: 66607
* Just make the Dwarf timer group static inside of the getter function. No ↵Bill Wendling2009-03-101-7/+5
| | | | | | need to alloc/dealloc. llvm-svn: 66591
* Don't put static functions in anonymous namespace.Bill Wendling2009-03-101-4/+0
| | | | llvm-svn: 66589
* These should *stop* the timer, not start it again.Bill Wendling2009-03-101-2/+2
| | | | llvm-svn: 66586
OpenPOWER on IntegriCloud