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| author | Sanjiv Gupta <sanjiv.gupta@microchip.com> | 2009-03-20 13:49:20 +0000 |
|---|---|---|
| committer | Sanjiv Gupta <sanjiv.gupta@microchip.com> | 2009-03-20 13:49:20 +0000 |
| commit | 83debdf4b4498936e81782ea7f723e56f0bc1f60 (patch) | |
| tree | 442e0d6c92785f1c1ff65dcaf9b79e8a84daf8c1 /llvm/lib/CodeGen | |
| parent | c035b7e8796936ea73262c91c3953e15d4a4faf4 (diff) | |
| download | bcm5719-llvm-83debdf4b4498936e81782ea7f723e56f0bc1f60.tar.gz bcm5719-llvm-83debdf4b4498936e81782ea7f723e56f0bc1f60.zip | |
Fixed build warnings for unused variables.
llvm-svn: 67372
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/Spiller.cpp | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/Spiller.cpp b/llvm/lib/CodeGen/Spiller.cpp index 2c96ddc2b96..efb3910f1ad 100644 --- a/llvm/lib/CodeGen/Spiller.cpp +++ b/llvm/lib/CodeGen/Spiller.cpp @@ -218,7 +218,6 @@ static bool InvalidateRegDef(MachineBasicBlock::iterator I, static void UpdateKills(MachineInstr &MI, BitVector &RegKills, std::vector<MachineOperand*> &KillOps, const TargetRegisterInfo* TRI) { - const TargetInstrDesc &TID = MI.getDesc(); for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || !MO.isUse()) @@ -881,7 +880,6 @@ void LocalSpiller::TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, } if (LastUDMI) { - const TargetInstrDesc &TID = LastUDMI->getDesc(); MachineOperand *LastUD = NULL; for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = LastUDMI->getOperand(i); @@ -944,7 +942,6 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, NextMII = next(MII); MachineInstr &MI = *MII; - const TargetInstrDesc &TID = MI.getDesc(); if (VRM.hasEmergencySpills(&MI)) { // Spill physical register(s) in the rare case the allocator has run out |
