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* Revert r340508: [DebugInfo] Fix bug in LiveDebugVariables.Chandler Carruth2018-08-231-10/+5
| | | | | | | | This patch's test case relies on debug prints which isn't generally an OK way to test stuff in LLVM and fails whenever asserts aren't enabled. I've send a heads-up to the commit and detailed comments on the review. llvm-svn: 340513
* [DebugInfo] Fix bug in LiveDebugVariables.Hsiangkai Wang2018-08-231-5/+10
| | | | | | | | | | | | | | | In lib/CodeGen/LiveDebugVariables.cpp, it uses std::prev(MBBI) to get DebugValue's SlotIndex. However, the previous instruction may be also a debug instruction. It could not use a debug instruction to query SlotIndex in mi2iMap. Scan all debug instructions and use the first debug instruction to query SlotIndex for following debug instructions. Only handle DBG_VALUE in handleDebugValue(). Differential Revision: https://reviews.llvm.org/D50621 llvm-svn: 340508
* [SelectionDAG] unroll unsupported vector FP ops earlier to avoid libcalls on ↵Sanjay Patel2018-08-221-7/+26
| | | | | | | | | | | | | | | | undef elements (PR38527) This solves the motivating case from: https://bugs.llvm.org/show_bug.cgi?id=38527 If we are legalizing an FP vector op that maps to 1 of the LLVM intrinsics that mimic libm calls, but we're going to end up with scalar libcalls for that vector type anyway, then we should unroll the vector op into scalars before widening. This avoids libcalls because we've lost the knowledge that some of the scalar elements are undef. Differential Revision: https://reviews.llvm.org/D50791 llvm-svn: 340469
* [ARM] Lower llvm.ctlz.i32 to a libcall when clz is not available.Eli Friedman2018-08-221-0/+15
| | | | | | | | | | The inline sequence is very long (about 70 bytes on Thumb1), so it's not really a good idea to inline it, especially when optimizing for size. Differential Revision: https://reviews.llvm.org/D47917 llvm-svn: 340458
* [SafeStack] Handle unreachable code with safe stack coloring.Eli Friedman2018-08-221-1/+3
| | | | | | | | | Instead of asserting that the function doesn't have any unreachable code, just ignore it for the purpose of computing liveness. Differential Revision: https://reviews.llvm.org/D51070 llvm-svn: 340456
* [CodeGenPrepare] Set debug locs when folding a comparison into a ↵Vedant Kumar2018-08-221-0/+4
| | | | | | | | | uadd.with.overflow CGP can replace a branch + select with a uadd.with.overflow. Teach it to set debug locations as it does this. llvm-svn: 340432
* [GISel]: Add legalization support for widening bit counting operationsAditya Nandakumar2018-08-221-0/+36
| | | | | | | | | | https://reviews.llvm.org/D51053 Added legalization for WidenScalar of various bitcounting opcodes. Reviewed by arsenm. llvm-svn: 340429
* [CodeGenPrepare] Set debug loc when widening a switch conditionVedant Kumar2018-08-221-0/+1
| | | | | | | Set a debug location on the cast instruction used to widen a switch condition. llvm-svn: 340379
* [CodeGenPrepare] Set debug locations when splitting selectsVedant Kumar2018-08-221-1/+5
| | | | | | | When splitting a select into a diamond, set debug locations on newly-created branch instructions and phi nodes. llvm-svn: 340371
* [CodeGenPrepare] Clean up dbg.value use-before-def as late as possibleVedant Kumar2018-08-211-5/+4
| | | | | | | | | | | CodeGenPrepare has a strategy for moving dbg.values so that a value's definition always dominates its debug users. This cleanup was happening too early (before certain CGP transforms were run), resulting in some dbg.value use-before-def errors. Perform this cleanup as late as possible to avoid use-before-def. llvm-svn: 340370
* [CodeGenPrepare] Scan past debug intrinsics to find select candidates (NFC)Vedant Kumar2018-08-211-3/+4
| | | | | | | | | | In optimizeSelectInst, when scanning for candidate selects to rewrite into branches, scan past debug intrinsics. This makes the debug-enabled and non-debug paths through optimizeSelectInst more congruent. NFC because every select is eventually visited either way. llvm-svn: 340368
* [CodeGenPrepare] Exit earlier when optimizing selects (NFC)Vedant Kumar2018-08-211-2/+5
| | | | | | | When optimizing for size, this allows optimizeSelectInst to skip a linear scan and exit early. llvm-svn: 340367
* MachineScheduler: Refactor setPolicy() to limit computing remaining latencyTom Stellard2018-08-211-28/+60
| | | | | | | | | | | | | | | | | | | | | Summary: Computing the remaining latency can be very expensive especially on graphs of N nodes where the number of edges approaches N^2. This reduces the compile time of a pathological case with the AMDGPU backend from ~7.5 seconds to ~3 seconds. This test case has a basic block with 2655 stores, each with somewhere between 500 and 1500 successors and predecessors. Reviewers: atrick, MatzeB, airlied, mareko Reviewed By: mareko Subscribers: tpr, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D50486 llvm-svn: 340346
* [WebAssembly] Don't make wasm cleanuppads into funclet entriesHeejin Ahn2018-08-211-3/+8
| | | | | | | | | | | | | | | Summary: Catchpads and cleanuppads are not funclet entries; they are only EH scope entries. We already dont't set `isEHFuncletEntry` for catchpads. This patch does the same thing for cleanuppads. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50654 llvm-svn: 340330
* [RegisterCoalescer] Use substPhysReg in reMaterializeTrivialDefBjorn Pettersson2018-08-211-1/+4
| | | | | | | | | | | | | | | | | | | Summary: When RegisterCoalescer::reMaterializeTrivialDef is substituting a register use in a DBG_VALUE instruction, and the old register is a subreg, and the new register is a physical register, then we need to use substPhysReg in order to extract the correct subreg. Reviewers: wmi, aprantl Reviewed By: wmi Subscribers: hiraditya, MatzeB, qcolombet, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D50844 llvm-svn: 340326
* [WebAssembly] Add isEHScopeReturn instruction propertyHeejin Ahn2018-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Summary: So far, `isReturn` property is used to mean both a return instruction from a functon and the end of an EH scope, a scope that starts with a EH scope entry BB and ends with a catchret or a cleanupret instruction. Because WinEH uses funclets, all EH-scope-ending instructions are also real return instruction from a function. But for wasm, they only serve as the end marker of an EH scope but not a return instruction that exits a function. This mismatch caused incorrect prolog and epilog generation in wasm EH scopes. This patch fixes this. This patch is in the same vein with rL333045, which splits `MachineBasicBlock::isEHFuncletEntry` into `isEHFuncletEntry` and `isEHScopeEntry`. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50653 llvm-svn: 340325
* [RegisterCoalscer] Manually remove leftover segments when commuting defKrzysztof Parzyszek2018-08-211-0/+12
| | | | | | | | | | | | | In removeCopyByCommutingDef, segments from the source live range are copied into (and merged with) the segments of the target live range. This is performed for all subranges of the source interval. It can happen that there will be subranges of the target interval that had no corresponding subranges in the source interval, and in such cases these subrages will not be updated. Since the copy being coalesced is about to be removed, these ranges need to be updated by removing the segments that are started by the copy. llvm-svn: 340318
* Update DBG_VALUE register operand during LiveInterval operationsYury Delendik2018-08-211-11/+11
| | | | | | | | | | | | | | | | | | | Summary: Handling of DBG_VALUE in ConnectedVNInfoEqClasses::Distribute() was fixed in PR16110. However DBG_VALUE register operands are not getting updated. This patch properly resolves the value location. Reviewers: MatzeB, vsk Reviewed By: MatzeB Subscribers: kparzysz, thegameg, vsk, MatzeB, dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D48994 llvm-svn: 340310
* Revert "Revert rr340111 "[GISel]: Add Legalization/lowering code for bit ↵Aditya Nandakumar2018-08-211-1/+122
| | | | | | | | | | | | | | | counting operations"" This reverts commit d1341152d91398e9a882ba2ee924147ea2f9b589. This patch originally made use of Nested MachineIRBuilder buildInstr calls, and since order of argument processing is not well defined, the instructions were built slightly in a different order (still correct). I've removed the nested buildInstr calls to have a defined order now. Patch was tested by Mikael. llvm-svn: 340309
* Change how finalizeBundle selects debug location for the BUNDLE instructionBjorn Pettersson2018-08-211-1/+11
| | | | | | | | | | | | | | | | | | | | | | Summary: Previously a BUNDLE instruction inherited the DebugLoc from the first instruction in the bundle, even if that DebugLoc had no DILocation. With this commit this is changed into selecting the first DebugLoc that has a DILocation, by searching among the bundled instructions. The idea is to reduce amount of bundles that are lacking debug locations. Reviewers: #debug-info, JDevlieghere Reviewed By: JDevlieghere Subscribers: JDevlieghere, mattd, llvm-commits Differential Revision: https://reviews.llvm.org/D50639 llvm-svn: 340267
* [DAGCombiner] Reduce load widths of shifted masksSam Parker2018-08-211-8/+41
| | | | | | | | | | | During combining, ReduceLoadWdith is used to combine AND nodes that mask loads into narrow loads. This patch allows the mask to be a shifted constant. This results in a narrow load which is then left shifted to compensate for the new offset. Differential Revision: https://reviews.llvm.org/D50432 llvm-svn: 340261
* [TargetLowering] Add BuildSDiv support for division by one or negone.Simon Pilgrim2018-08-211-15/+27
| | | | | | This reduces most of the sdiv stages (the MULHS, shifts etc.) to just zero/identity values and use the numerator scale factor to multiply by +1/-1. llvm-svn: 340260
* [RegisterCoalescer] Do not assert when trying to remat dead valuesBjorn Pettersson2018-08-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: RegisterCoalescer::reMaterializeTrivialDef used to assert that the input register was live in. But as shown by the new coalesce-dead-lanes.mir test case that seems to be a valid scenario. We now return false instead of the assert, simply avoiding to remat the dead def. Normally a COPY of an undef value is eliminated by eliminateUndefCopy(). Although we only do that when the destination isn't a physical register. So the situation above should be limited to the case when we copy an undef value to a physical register. Reviewers: kparzysz, wmi, tpr Reviewed By: kparzysz Subscribers: MatzeB, qcolombet, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D50842 llvm-svn: 340255
* Consistently use MemoryLocation::UnknownSize to indicate unknown access sizeKrzysztof Parzyszek2018-08-206-16/+37
| | | | | | | | | | | | 1. Change the software pipeliner to use unknown size instead of dropping memory operands. It used to do it before, but MachineInstr::mayAlias did not handle it correctly. 2. Recognize UnknownSize in MachineInstr::mayAlias. 3. Print and parse UnknownSize in MIR. Differential Revision: https://reviews.llvm.org/D50339 llvm-svn: 340208
* [FPEnv] Support constrained FREM intrinsicCameron McInally2018-08-203-0/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
* [PSV] Update API to be able to use TargetCustom without UB.Marcello Maggioni2018-08-201-2/+2
| | | | | | | | | | | getTargetCustom() requires values for "Kind" in the constructor that are not in the PSVKind enum. Passing a value that is not inside an enum as an argument to a constructor of the type of the enum is UB. Changing to the underlying type of the enum would solve the UB Differential Revision: https://reviews.llvm.org/D50909 llvm-svn: 340200
* Revert "Revert r339977: [GISel]: Add Opcodes for a few LLVM Intrinsics"Aditya Nandakumar2018-08-201-0/+10
| | | | | | | | | | This reverts commit 7debc334e6421bb5251ef8f18e97166dfc7dd787. I missed updating legalizer-info-validation.mir as I had assertions turned off in my build and that specific test requires asserts. Fixed it now. llvm-svn: 340197
* [TargetLowering] Disable BuildSDiv division by one or negone.Simon Pilgrim2018-08-201-1/+2
| | | | | | Fuzz tests have detected an issue, currently working on a fix. llvm-svn: 340195
* Revert rr340111 "[GISel]: Add Legalization/lowering code for bit counting ↵Reid Kleckner2018-08-201-121/+1
| | | | | | | | operations" It causes LegalizerHelperTest.LowerBitCountingCTTZ1 to fail. llvm-svn: 340186
* [SelectionDAG] Reuse the Op's VT. NFCI.Simon Pilgrim2018-08-201-2/+2
| | | | llvm-svn: 340173
* [SelectionDAG] Add partial sign-bit support to ComputeNumSignBits for ↵Simon Pilgrim2018-08-201-2/+16
| | | | | | | | | | BITCAST nodes Only adds support to the existing 'large element' scalar/vector to 'small element' vector bitcasts. Handle the case where the sign bit extends to only part of the small elements. llvm-svn: 340169
* [SelectionDAG] Add basic demanded elements support to ComputeNumSignBits for ↵Simon Pilgrim2018-08-191-1/+8
| | | | | | | | | | BITCAST nodes Only adds support to the existing 'large element' scalar/vector to 'small element' vector bitcasts. The next step would be to support cases where the large elements aren't all sign bits, and determine the small element equivalent based on the demanded elements. llvm-svn: 340143
* [DebugInfo] In FastISel, convert llvm.dbg.label to DBG_LABEL MI.Hsiangkai Wang2018-08-181-0/+12
| | | | | | | | Convert llvm.dbg.label(!label_metadata) to DBG_LABEL !label_metadata. Differential Revision: https://reviews.llvm.org/D50622 llvm-svn: 340122
* [DAGCombiner] Allow divide by constant optimization on opaque constants.Craig Topper2018-08-181-2/+2
| | | | | | | | | | | | | | | | | Summary: I believe this restores the behavior we had before r339147. Fixes PR38622. Reviewers: RKSimon, chandlerc, spatel Reviewed By: chandlerc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D50936 llvm-svn: 340120
* [GISel]: Add Legalization/lowering code for bit counting operationsAditya Nandakumar2018-08-181-1/+121
| | | | | | | | | | https://reviews.llvm.org/D48847#inline-448257 Ported legalization expansions for CTLZ/CTTZ from DAG to GISel. Reviewed by rtereshin. llvm-svn: 340111
* DAG: Fix isKnownNeverNaN for basic non-sNaN casesMatt Arsenault2018-08-171-12/+7
| | | | | | | fadd/fsub/fmul need to worry about infinities as well as fdiv. llvm-svn: 340085
* [DebugInfo] Generate DWARF debug information for labels. (Fix leak problems)Hsiangkai Wang2018-08-1716-149/+407
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two forms for label debug information in DWARF format. 1. Labels in a non-inlined function: DW_TAG_label DW_AT_name DW_AT_decl_file DW_AT_decl_line DW_AT_low_pc 2. Labels in an inlined function: DW_TAG_label DW_AT_abstract_origin DW_AT_low_pc We will collect label information from DBG_LABEL. Before every DBG_LABEL, we will generate a temporary symbol to denote the location of the label. The symbol could be used to get DW_AT_low_pc afterwards. So, we create a mapping between 'inlined label' and DBG_LABEL MachineInstr in DebugHandlerBase. The DBG_LABEL in the mapping is used to query the symbol before it. The AbstractLabels in DwarfCompileUnit is used to process labels in inlined functions. We also keep a mapping between scope and labels in DwarfFile to help to generate correct tree structure of DIEs. It also generates label debug information under global isel. Differential Revision: https://reviews.llvm.org/D45556 llvm-svn: 340039
* [AtomicExpandPass] Widen partword atomicrmw or/xor/and before tryExpandAtomicRMWAlex Bradbury2018-08-171-4/+48
| | | | | | | | | | | | | | | | | | | This patch performs a widening transformation of bitwise atomicrmw {or,xor,and} and applies it prior to tryExpandAtomicRMW. This operates similarly to convertCmpXchgToIntegerType. For these operations, the i8/i16 atomicrmw can be implemented in terms of the 32-bit atomicrmw by appropriately manipulating the operands. There is no functional change for the handling of partword or/xor, but the transformation for partword 'and' is new. The advantage of performing this transformation early is that the same code-path can be used regardless of the approach used to expand the atomicrmw (AtomicExpansionKind). i.e. the same logic is used for AtomicExpansionKind::CmpXchg and can also be used by the intrinsic-based expansion in D47882. Differential Revision: https://reviews.llvm.org/D48129 llvm-svn: 340027
* [DAGCombiner] extractShiftForRotate - fix out of range shift issueSimon Pilgrim2018-08-171-2/+2
| | | | | | | | | Don't just check for negative shift amounts. Fixes OSS Fuzz #9935 https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=9935 llvm-svn: 340015
* [DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) foldingSimon Pilgrim2018-08-171-17/+16
| | | | | | | | Add support for cases where only some c1+c2 results exceed the max bitshift, clamping accordingly. Differential Revision: https://reviews.llvm.org/D35722 llvm-svn: 340010
* Fix "control reaches end of non-void function" -Wreturn-type warning. NFCI.Simon Pilgrim2018-08-171-0/+1
| | | | llvm-svn: 340006
* [MISC]Fix wrong usage of std::equal()Chen Zheng2018-08-171-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D49958 llvm-svn: 340000
* Revert r339977: [GISel]: Add Opcodes for a few LLVM IntrinsicsChandler Carruth2018-08-171-10/+0
| | | | | | This is breaking ~all the bots. llvm-svn: 339982
* [GISel]: Add Opcodes for a few LLVM IntrinsicsAditya Nandakumar2018-08-171-0/+10
| | | | | | | | | | | https://reviews.llvm.org/D50401 Add opcodes for llvm.intrinsic.trunc, round, and update the IRTranslator for the same. Reviewed by: dsanders. llvm-svn: 339977
* DebugInfo: Remove command line (& target-based) disabling of pubnames in ↵David Blaikie2018-08-163-14/+2
| | | | | | | | | favor of metadata Now that Clang disables NVPTX pubnames via metadata there's no need for this fallback to target detection in the backend. llvm-svn: 339970
* [x86/MIR] Implement support for pre- and post-instruction symbols, asChandler Carruth2018-08-166-29/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | well as MIR parsing support for `MCSymbol` `MachineOperand`s. The only real way to test pre- and post-instruction symbol support is to use them in operands, so I ended up implementing that within the patch as well. I can split out the operand support if folks really want but it doesn't really seem worth it. The functional implementation of pre- and post-instruction symbols is now *completely trivial*. Two tiny bits of code in the (misnamed) AsmPrinter. It should be completely target independent as well. We emit these exactly the same way as we emit basic block labels. Most of the code here is to give full dumping, MIR printing, and MIR parsing support so that we can write useful tests. The MIR parsing of MC symbol operands still isn't 100%, as it forces the symbols to be non-temporary and non-local symbols with names. However, those names often can encode most (if not all) of the special semantics desired, and unnamed symbols seem especially annoying to serialize and de-serialize. While this isn't perfect or full support, it seems plenty to write tests that exercise usage of these kinds of operands. The MIR support for pre-and post-instruction symbols was quite straightforward. I chose to print them out in an as-if-operand syntax similar to debug locations as this seemed the cleanest way and let me use nice introducer tokens rather than inventing more magic punctuation like we use for memoperands. However, supporting MIR-based parsing of these symbols caused me to change the design of the symbol support to allow setting arbitrary symbols. Without this, I don't see any reasonable way to test things with MIR. Differential Revision: https://reviews.llvm.org/D50833 llvm-svn: 339962
* [DAGCombiner] Don't reassociate operations that have the vector reduction ↵Craig Topper2018-08-161-9/+13
| | | | | | | | | | | | | | flag set. When nodes are reassociated the vector-reduction flag gets lost. The test case is here is what would happen if you had a sum of absolute differences loop that started with a non-zero but contant sum and that loop was unrolled. The vectorizer will generate a constant vector for the initial value. And DAGCombiner reassociate tries to move it down the addition tree erasing the vector-reduction flag. Interestingly this moves constants the opposite direction of the reassociate IR pass. I've chosen to just punt on the reassociate, but I suppose we could maybe preserve the flag if both nodes have it set. Differential Revision: https://reviews.llvm.org/D50827 llvm-svn: 339946
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-1612-162/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a generically extensible collection of extra info attached to a `MachineInstr`. The primary change here is cleaning up the APIs used for setting and manipulating the `MachineMemOperand` pointer arrays so chat we can change how they are allocated. Then we introduce an extra info object that using the trailing object pattern to attach some number of MMOs but also other extra info. The design of this is specifically so that this extra info has a fixed necessary cost (the header tracking what extra info is included) and everything else can be tail allocated. This pattern works especially well with a `BumpPtrAllocator` which we use here. I've also added the basic scaffolding for putting interesting pointers into this, namely pre- and post-instruction symbols. These aren't used anywhere yet, they're just there to ensure I've actually gotten the data structure types correct. I'll flesh out support for these in a subsequent patch (MIR dumping, parsing, the works). Finally, I've included an optimization where we store any single pointer inline in the `MachineInstr` to avoid the allocation overhead. This is expected to be the overwhelmingly most common case and so should avoid any memory usage growth due to slightly less clever / dense allocation when dealing with >1 MMO. This did require several ergonomic improvements to the `PointerSumType` to reasonably support the various usage models. This also has a side effect of freeing up 8 bits within the `MachineInstr` which could be repurposed for something else. The suggested direction here came largely from Hal Finkel. I hope it was worth it. ;] It does hopefully clear a path for subsequent extensions w/o nearly as much leg work. Lots of thanks to Reid and Justin for careful reviews and ideas about how to do all of this. Differential Revision: https://reviews.llvm.org/D50701 llvm-svn: 339940
* DebugInfo: Add metadata support for disabling DWARF pub sectionsDavid Blaikie2018-08-165-38/+68
| | | | | | | | | | | | | | | | | | | | | | | In cases where the debugger load time is a worthwhile tradeoff (or less costly - such as loading from a DWP instead of a variety of DWOs (possibly over a high-latency/distributed filesystem)) against object file size, it can be reasonable to disable pubnames and corresponding gdb-index creation in the linker. A backend-flag version of this was implemented for NVPTX in D44385/r327994 - which was fine for NVPTX which wouldn't mix-and-match CUs. Now that it's going to be a user-facing option (likely powered by "-gno-pubnames", the same as GCC) it should be encoded in the DICompileUnit so it can vary per-CU. After this, likely the NVPTX support should be migrated to the metadata & the previous flag implementation should be removed. Reviewers: aprantl Differential Revision: https://reviews.llvm.org/D50213 llvm-svn: 339939
* [MachineVerifier] Check if predecessor is jointly dominated by undefsKrzysztof Parzyszek2018-08-161-1/+11
| | | | | | | | Each use of a value should be jointly dominated by the union of defs and undefs. It can happen that it will only be jointly dominated by undefs, and that is still legal. Make sure that the verifier is aware of that. llvm-svn: 339924
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