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authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-08-20 13:44:03 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-08-20 13:44:03 +0000
commit1a00042270d34e8cb9d04da2de454ba5489a76e1 (patch)
treec40eefd03d485ff7120fc7a2dfadc8391cd76f5f /llvm/lib/CodeGen
parent216a2da5774d50571e97a67928b0ca710545161c (diff)
downloadbcm5719-llvm-1a00042270d34e8cb9d04da2de454ba5489a76e1.tar.gz
bcm5719-llvm-1a00042270d34e8cb9d04da2de454ba5489a76e1.zip
[SelectionDAG] Reuse the Op's VT. NFCI.
llvm-svn: 340173
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c40fda3a20b..9e5ad9c1685 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3244,7 +3244,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
// Bitcast 'large element' scalar/vector to 'small element' vector.
if ((SrcBits % VTBits) == 0) {
- assert(Op.getValueType().isVector() && "Expected bitcast to vector");
+ assert(VT.isVector() && "Expected bitcast to vector");
unsigned Scale = SrcBits / VTBits;
APInt SrcDemandedElts(NumElts / Scale, 0);
@@ -3382,7 +3382,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
// If setcc returns 0/-1, all bits are sign bits.
// We know that we have an integer-based boolean since these operations
// are only available for integer.
- if (TLI->getBooleanContents(Op.getValueType().isVector(), false) ==
+ if (TLI->getBooleanContents(VT.isVector(), false) ==
TargetLowering::ZeroOrNegativeOneBooleanContent)
return VTBits;
break;
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