summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
...
* Immediately erase trivially useless copies.Jakob Stoklund Olesen2012-05-191-2/+4
| | | | | | | There is no need for these instructions to stick around since they are known to be not dead. llvm-svn: 157102
* Run proper recursive dead code elimination during coalescing.Jakob Stoklund Olesen2012-05-192-21/+63
| | | | | | | | | | | | | | | Dead copies cause problems because they are trivial to coalesce, but removing them gived the live range a dangling end point. This patch enables full dead code elimination which trims live ranges to their uses so end points don't dangle. DCE may erase multiple instructions. Put the pointers in an ErasedInstrs set so we never risk visiting erased instructions in the work list. There isn't supposed to be any dead copies entering RegisterCoalescer, but they do slip by as evidenced by test/CodeGen/X86/coalescer-dce.ll. llvm-svn: 157101
* Allow LiveRangeEdit to be created with a NULL parent.Jakob Stoklund Olesen2012-05-194-9/+9
| | | | | | The dead code elimination with callbacks is still useful. llvm-svn: 157100
* Modernize naming convention for class members.Jakob Stoklund Olesen2012-05-181-20/+20
| | | | | | No functional change. llvm-svn: 157079
* Move all work list processing to copyCoalesceWorkList().Jakob Stoklund Olesen2012-05-181-39/+42
| | | | | | This will make it possible to filter out erased instructions later. llvm-svn: 157073
* Refactor data-in-code annotations.Jim Grosbach2012-05-181-12/+1
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Remove duplicate code that we could just fallthrough to.Eric Christopher2012-05-181-1/+0
| | | | llvm-svn: 157060
* Simplify RegisterCoalescer::copyCoalesceInMBB().Jakob Stoklund Olesen2012-05-181-48/+15
| | | | | | | | | It is no longer necessary to separate VirtCopies, PhysCopies, and ImpDefCopies. Implicitly defined copies are extremely rare after we added the ProcessImplicitDefs pass, and physical register copies are not joined any longer. llvm-svn: 157059
* Remove support for PhysReg joining.Jakob Stoklund Olesen2012-05-181-136/+14
| | | | | | | | | | | | | | | | | | | | | | | | This has been disabled for a while, and it is not a feature we want to support. Copies between physical and virtual registers are eliminated by good hinting support in the register allocator. Joining virtual and physical registers is really a form of register allocation, and the coalescer is not properly equipped to do that. In particular, it cannot backtrack coalescing decisions, and sometimes that would cause it to create programs that were impossible to register allocate, by exhausting a small register class. It was also very difficult to keep track of the live ranges of aliasing registers when extending the live range of a physreg. By disabling physreg joining, we can let fixed physreg live ranges remain constant throughout the register allocator super-pass. One type of physreg joining remains: A virtual register that has a single value which is a copy of a reserved register can be merged into the reserved physreg. This always lowers register pressure, and since we don't compute live ranges for reserved registers, there are no problems with aliases. llvm-svn: 157055
* Recommited reworked r156804:Stepan Dyatkovskiy2012-05-182-53/+29
| | | | | | SelectionDAGBuilder::Clusterify : main functinality was replaced with CRSBuilder::optimize, so big part of Clusterify's code was reduced. llvm-svn: 157046
* Teach two-address pass to update the "source" map so it doesn't perform aEvan Cheng2012-05-181-1/+7
| | | | | | | | | non-profitable commute using outdated info. The test case would still fail because of poor pre-RA schedule. That will be fixed by MI scheduler. rdar://11472010 llvm-svn: 157038
* commentsAndrew Trick2012-05-171-2/+3
| | | | llvm-svn: 157020
* misched: trace ReadyQ.Andrew Trick2012-05-171-0/+8
| | | | llvm-svn: 157007
* misched: Added 3-level regpressure back-off.Andrew Trick2012-05-173-75/+288
| | | | | | | | | | | | | | | | | | Introduce the basic strategy for register pressure scheduling. 1) Respect target limits at all times. 2) Indentify critical register classes (pressure sets). Track pressure within the scheduled region. Avoid increasing scheduled pressure for critical registers. 3) Avoid exceeding the max pressure of the region prior to scheduling. Added logic for picking between the top and bottom ready Q's based on regpressure heuristics. Status: functional but needs to be asjusted to achieve good results. llvm-svn: 157006
* commentAndrew Trick2012-05-172-3/+1
| | | | llvm-svn: 157005
* regpressure: Fix getMaxUpwardPressureDelta.Andrew Trick2012-05-171-2/+6
| | | | llvm-svn: 157004
* misched: fix liveness iteratorsAndrew Trick2012-05-171-10/+16
| | | | llvm-svn: 157003
* whitespaceAndrew Trick2012-05-172-2/+3
| | | | llvm-svn: 157002
* Never clear <undef> flags on already joined copies.Jakob Stoklund Olesen2012-05-171-4/+6
| | | | | | | | | | | | | | | | | | | | | RegisterCoalescer set <undef> flags on all operands of copy instructions that are scheduled to be removed. This is so they won't affect shrinkToUses() by introducing false register reads. Make sure those <undef> flags are never cleared, or shrinkToUses() could cause live intervals to end at instructions about to be deleted. This would be a lot simpler if RegisterCoalescer could just erase joined copies immediately instead of keeping all the to-be-deleted instructions around. This fixes PR12862. Unfortunately, bugpoint can't create a sane test case for this. Like many other coalescer problems, this failure depends of a very fragile series of events. <rdar://problem/11474428> llvm-svn: 157001
* Fix a verifier bug.Jakob Stoklund Olesen2012-05-171-1/+1
| | | | | | Make sure useless (def-only) intervals also get verified. llvm-svn: 157000
* Relax the requirement that the exception object must be an instruction. DuringBill Wendling2012-05-171-6/+6
| | | | | | bugpoint-ing, it may turn into something else. llvm-svn: 156998
* SelectionDAGBuilder: CaseBlock, CaseRanges and CaseCmp changed ↵Stepan Dyatkovskiy2012-05-172-10/+11
| | | | | | representation of Low and High from signed to unsigned. Since unsigned ints usually simpler, faster and allows to reduce some extra signed bit checks needed before <,>,<=,>= comparisons. llvm-svn: 156985
* Set sub-register <undef> flags more accurately.Jakob Stoklund Olesen2012-05-161-7/+11
| | | | | | | | | | | | | | | When widening an existing <def,reads-undef> operand to a super-register, it may be necessary to clear the <undef> flag because the wider register is now read-modify-write through the instruction. Conversely, it may be necessary to add an <undef> flag when the coalescer turns a full-register def into a sub-register def, but the larger register wasn't live before the instruction. This happens in test/CodeGen/ARM/coalesce-subregs.ll, but the test is too small for the <undef> flags to affect the generated code. llvm-svn: 156951
* Fix a thinko in DisintegrateMERGE_VALUES. Patch by Xiaoyi Guo.Duncan Sands2012-05-162-2/+2
| | | | llvm-svn: 156909
* Enable sub-sub-register copy coalescing.Jakob Stoklund Olesen2012-05-151-9/+0
| | | | | | | | | | | | | | | | It is now possible to coalesce weird skewed sub-register copies by picking a super-register class larger than both original registers. The included test case produces code like this: vld2.32 {d16, d17, d18, d19}, [r0]! vst2.32 {d18, d19, d20, d21}, [r0] We still perform interference checking as if it were a normal full copy join, so this is still quite conservative. In particular, the f1 and f2 functions in the included test case still have remaining copies because of false interference. llvm-svn: 156878
* Teach RegisterCoalescer to handle symmetric sub-register copies.Jakob Stoklund Olesen2012-05-151-14/+28
| | | | | | | | | | | | | It is possible to coalesce two overlapping registers to a common super-register that it larger than both of the original registers. The important difference is that it may be necessary to rewrite DstReg operands as well as SrcReg operands because the sub-register index has changed. This behavior is still disabled by CoalescerPair. llvm-svn: 156869
* Handle NewReg==OldReg in renameRegister().Jakob Stoklund Olesen2012-05-151-1/+2
| | | | | | | This can happen when widening a virtual register to a super-register class. llvm-svn: 156867
* We never call adjustCopiesBackFrom() for partial copies.Jakob Stoklund Olesen2012-05-151-1/+3
| | | | | | There is no need to look at an always null SrcIdx. llvm-svn: 156866
* Extend the CoalescerPair interface to handle symmetric sub-register copies.Jakob Stoklund Olesen2012-05-152-44/+51
| | | | | | | | | | Now both SrcReg and DstReg can be sub-registers of the final coalesced register. CoalescerPair::setRegisters still rejects such copies because RegisterCoalescer doesn't yet handle them. llvm-svn: 156848
* Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside ↵Andrew Trick2012-05-151-22/+243
| | | | | | | | | | | | | | | MachineScheduler. This feature avoids creating edges in the scheduler's dependence graph for non-aliasing memory operations according to whichever alias analysis is available. It has been fully tested in Hexagon. Before making this default, it needs to be extended to handle multiple MachineMemOperands, compile time needs more evaluation, and benchmarking on X86 and ARM is needed. Patch by Sergei Larin! llvm-svn: 156842
* Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach2012-05-151-5/+8
| | | | | | | | Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
* Rejected r156804 due to buildbots failures.Stepan Dyatkovskiy2012-05-151-35/+46
| | | | llvm-svn: 156808
* SelectionDAGBuilder::Clusterify : main functinality was replaced with ↵Stepan Dyatkovskiy2012-05-151-46/+35
| | | | | | CRSBuilder::optimize, so big part of Clusterify's code was reduced. llvm-svn: 156804
* Don't access MO reference after invalidating operand list.Jakob Stoklund Olesen2012-05-141-2/+3
| | | | | | This should unbreak llvm-x86_64-linux. llvm-svn: 156778
* Fix PR12821.Jakob Stoklund Olesen2012-05-141-0/+6
| | | | | | | RAFast must add an <imp-def> operand when it is rewriting a sub-register def that isn't a read-modify-write. llvm-svn: 156777
* Rename @llvm.debugger to @llvm.debugtrap.Dan Gohman2012-05-142-3/+3
| | | | llvm-svn: 156774
* Don't look for empty live ranges in the unions.Jakob Stoklund Olesen2012-05-121-1/+4
| | | | | | | | | Empty live ranges represent undef and still get allocated, but they won't appear in LiveIntervalUnions. Patch by Patrik Hägglund! llvm-svn: 156685
* Revert 156658.Chad Rosier2012-05-111-2/+1
| | | | llvm-svn: 156662
* [fast-isel] Fast-isel doesn't use the expect intrinsic.Chad Rosier2012-05-111-1/+2
| | | | llvm-svn: 156658
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-111-0/+9
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-112-0/+5
| | | | | | but it generates int3 on x86 instead of ud2. llvm-svn: 156593
* misched: Print machineinstrs with -debug-only=mischedAndrew Trick2012-05-101-0/+2
| | | | llvm-svn: 156576
* misched: tracing register pressure heuristics.Andrew Trick2012-05-101-6/+22
| | | | llvm-svn: 156575
* misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick2012-05-101-38/+144
| | | | | | | | | | | Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. llvm-svn: 156574
* misched: Release only unscheduled nodes into ReadyQ.Andrew Trick2012-05-101-2/+8
| | | | llvm-svn: 156573
* misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick2012-05-101-11/+44
| | | | llvm-svn: 156572
* misched: Introducing Top and Bottom register pressure trackers during ↵Andrew Trick2012-05-103-39/+112
| | | | | | scheduling. llvm-svn: 156571
* RegPressure: API for speculatively checking instruction pressure.Andrew Trick2012-05-102-1/+229
| | | | | | | | | Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the tracker by speculatively handling an instruction out of order. But it is convenient for now. In the future, we will cache each instruction's pressure contribution to make this efficient. llvm-svn: 156561
* RegPressure: fix array index iteration style.Andrew Trick2012-05-101-8/+8
| | | | llvm-svn: 156560
* Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren2012-05-101-9/+0
| | | | | | This commit broke an external linux bot and gave a compile-time warning. llvm-svn: 156556
OpenPOWER on IntegriCloud