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* change printStringChar to emit characters as unsigned char instead of char,Chris Lattner2009-04-081-9/+5
| | | | | | | | | | | avoiding sign extension for the top octet. For "negative" chars, we'd print stuff like: .asciz "\702... now we print: .asciz "\302... llvm-svn: 68577
* Implement support for using modeling implicit-zero-extension on x86-64Dan Gohman2009-04-086-53/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
* Revert prev. patch for now.Devang Patel2009-04-071-4/+6
| | | | llvm-svn: 68569
* Right now DBG_LABEL are required for llvm.dbg.region_start and ↵Devang Patel2009-04-071-6/+4
| | | | | | llvm.dbg.region_end in non-fast mode also. llvm-svn: 68559
* Don't attempt to handle aggregate argument values in FastISel; letDan Gohman2009-04-071-1/+5
| | | | | | SelectionDAG do those. This fixes PR3955. llvm-svn: 68546
* Fix a TargetLowering optimization so that it doesn't duplicateDan Gohman2009-04-031-0/+1
| | | | | | loads when an input node has multiple uses. llvm-svn: 68398
* Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.Dan Gohman2009-04-032-20/+0
| | | | | | | Note that these are distinct from TargetInstrInfo::INSERT_SUBREG and TargetInstrInfo::EXTRACT_SUBREG, which are used. llvm-svn: 68355
* To convert the StopPoint insn into an assembler directive by ISel, we need ↵Sanjiv Gupta2009-04-021-0/+4
| | | | | | to have access to the line number field. So we convert that info as an operand by custom handling DBG_STOPPOINT in legalize. llvm-svn: 68329
* Fully general expansion of integer shift of any size.Evan Cheng2009-03-312-3/+81
| | | | llvm-svn: 68134
* Reapply 68073, with fixes. EH Landing-pad basic blocks are notDan Gohman2009-03-311-0/+10
| | | | | | | | entered via fall-through. Don't miss fallthroughs from blocks terminated by conditional branches. Also, move isOnlyReachableByFallthrough out of line. llvm-svn: 68129
* Minor top-level comment fix.Dan Gohman2009-03-311-1/+1
| | | | llvm-svn: 68113
* Oy! When reverting r68073, I added in experimental code. Sorry...Bill Wendling2009-03-314-95/+32
| | | | llvm-svn: 68099
* Remove the "fast" cases for spill and restore point determination, as these ↵Owen Anderson2009-03-311-126/+59
| | | | | | | | were subtlely wrong in obscure cases. Patch the testcase to account for this change. llvm-svn: 68093
* Revert r68073. It's causing a failure in the Apple-style builds.Bill Wendling2009-03-314-32/+95
| | | | llvm-svn: 68092
* Fix live-out reg logic to not insert over-aggressive AssertZExtDan Gohman2009-03-311-3/+3
| | | | | | instructions. This fixes lua. llvm-svn: 68083
* Turn a 2-address instruction into a 3-address one when it's profitable even ↵Evan Cheng2009-03-301-21/+68
| | | | | | | | | | | | | if the two-address operand is killed. e.g. %reg1024<def> = MOV r1 %reg1025<def> = ADD %reg1024, %reg1026 r0 = MOV %reg1025 If it's not possible / profitable to commute ADD, then turning ADD into a LEA saves a copy. llvm-svn: 68065
* Balance out quote in debug output.Bill Wendling2009-03-301-1/+1
| | | | llvm-svn: 68059
* Fix grammar-o in comment.Bill Wendling2009-03-301-1/+1
| | | | llvm-svn: 68057
* Constify arguments in isSuccessor and isLayoutSuccessor.Dan Gohman2009-03-301-2/+2
| | | | llvm-svn: 68054
* Fix PR3899: add support for extracting floats from vectorsDuncan Sands2009-03-293-0/+22
| | | | | | | when using -soft-float. Based on a patch by Jakob Stoklund Olesen. llvm-svn: 67996
* Make check in CheckTailCallReturnConstraints for ignorable instructions betweenArnold Schwaighofer2009-03-281-18/+32
| | | | | | | a CALL and a RET node more generic. Add a test for tail calls with a void return. llvm-svn: 67943
* Enable tail call optimization for functions that return a struct (bug 3664) ↵Arnold Schwaighofer2009-03-281-0/+24
| | | | | | and for functions that return types that need extending (e.g i1). llvm-svn: 67934
* Optimize some 64-bit multiplication by constants into two lea's or one lea + ↵Evan Cheng2009-03-281-8/+8
| | | | | | | | | | | | | | | | | shl since imulq is slow (latency 5). e.g. x * 40 => shlq $3, %rdi leaq (%rdi,%rdi,4), %rax This has the added benefit of allowing more multiply to be folded into addressing mode. e.g. a * 24 + b => leaq (%rdi,%rdi,2), %rax leaq (%rsi,%rax,8), %rax llvm-svn: 67917
* Fix what surely must be a copy+pasto.Dan Gohman2009-03-271-2/+2
| | | | llvm-svn: 67881
* Initialize LiveOutInfo's APInt members to zero, as APInt'sDan Gohman2009-03-271-1/+1
| | | | | | | default constructor produces an uninitialized APInt. This fixes PR3896. llvm-svn: 67879
* Shrink wrapping in PEI: initial release. Finishing development, enable with ↵John Mosby2009-03-271-43/+913
| | | | | | --shrink-wrap. llvm-svn: 67828
* Don't assign a new stack slot if the pre-alloc splitter already assigned one.Owen Anderson2009-03-261-2/+9
| | | | llvm-svn: 67764
* Pull transform from target-dependent code into target-independent code.Bill Wendling2009-03-261-0/+49
| | | | llvm-svn: 67742
* Revert 67132. This is breaking some objective-c apps.Evan Cheng2009-03-251-3/+13
| | | | | | Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext. llvm-svn: 67701
* When optimizing with debug info, don't keep theDale Johannesen2009-03-251-4/+5
| | | | | | | | stoppoint nodes around until Legalize; doing this imposed an ordering on a sequence of loads that came from different lines, interfering with scheduling. llvm-svn: 67692
* CodeGen still defaults to non-verbose asm, but llc now overrides it and ↵Evan Cheng2009-03-253-7/+18
| | | | | | default to verbose. llvm-svn: 67668
* Do not ignore DW_TAG_class_type!Devang Patel2009-03-251-0/+1
| | | | llvm-svn: 67661
* Fix PR3845: Avoid stale MachineInstruction pointer reference.Evan Cheng2009-03-241-3/+1
| | | | llvm-svn: 67649
* more tidying: name the components of PhysReg in the case whenChris Lattner2009-03-241-8/+9
| | | | | | the target constraint specifies a specific physreg. llvm-svn: 67618
* Tidy a bit more.Chris Lattner2009-03-241-3/+3
| | | | llvm-svn: 67617
* simplify this code a bit now that "allocation to a vreg class" can neverChris Lattner2009-03-241-16/+13
| | | | | | fail. llvm-svn: 67616
* Minor compile-time optimization; don't bother checkingDan Gohman2009-03-241-1/+1
| | | | | | | canClobberPhysRegDefs if the successor node doesn't clobber any physical registers. llvm-svn: 67587
* Add a pre-pass to the burr-list scheduler which makes adjustments toDan Gohman2009-03-241-0/+120
| | | | | | | | | help out the register pressure reduction heuristics in the case of nodes with multiple uses. Currently this uses very conservative heuristics, so it doesn't have a broad impact, but in cases where it does help it can make a big difference. llvm-svn: 67586
* Do not emit comments unless -asm-verbose.Evan Cheng2009-03-241-93/+150
| | | | llvm-svn: 67580
* Fix a bug in spill weight computation. If the alias is a super-register, and ↵Evan Cheng2009-03-231-7/+34
| | | | | | | | | | | the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases. e.g. allocating for GR32, bh is not used, updating bl spill weight. bl should get the same spill weight otherwise it will be choosen as a spill candidate since spilling bh doesn't make ebx available. This fix PR2866. llvm-svn: 67574
* Fix internal representation of fp80 to be theDale Johannesen2009-03-231-8/+8
| | | | | | | | | | same as a normal i80 {low64, high16} rather than its own {high64, low16}. A depressing number of places know about this; I think I got them all. Bitcode readers and writers convert back to the old form to avoid breaking compatibility. llvm-svn: 67562
* When unfolding a load during scheduling, the new operator node hasDan Gohman2009-03-231-3/+6
| | | | | | | | | | a data dependency on the load node, so it really needs a data-dependence edge to the load node, even if the load previously existed. And add a few comments. llvm-svn: 67554
* Fix PR3391 and PR3864. Reg allocator infinite looping.Evan Cheng2009-03-232-6/+14
| | | | llvm-svn: 67544
* Don't set SUnit::hasPhysRegDefs to true unless the defs areDan Gohman2009-03-231-1/+4
| | | | | | actually have uses, which reflects the way it's used. llvm-svn: 67540
* Fix canClobberPhysRegDefs to check all SDNodes grouped togetherDan Gohman2009-03-231-14/+19
| | | | | | | in an SUnit, instead of just the first one. This fix is needed by some upcoming scheduler changes. llvm-svn: 67531
* Add a new bit to SUnit to record whether a node has implicit physregDan Gohman2009-03-231-3/+6
| | | | | | defs, regardless of whether they are actually used. llvm-svn: 67528
* Now that errs() is properly non-buffered, there's no need toDan Gohman2009-03-233-4/+2
| | | | | | explicitly flush it. llvm-svn: 67526
* Model inline asm constraint which ties an input to an output register as ↵Evan Cheng2009-03-234-38/+92
| | | | | | machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. llvm-svn: 67512
* Do not fold away subreg_to_reg if the source register has a sub-register ↵Evan Cheng2009-03-231-3/+9
| | | | | | | | | | index. That means the source register is taking a sub-register of a larger register. e.g. On x86 %RAX<def> = ... %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3 The first def is defining RAX, not EAX so the top bits were not zero-extended. llvm-svn: 67511
* Simplify this code; use a while instead of an if and a do-while.Dan Gohman2009-03-201-9/+6
| | | | llvm-svn: 67400
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