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* Make Intel syntax mode friendlier to Microsoft ML assembler (still needs ↵Jeff Cohen2006-05-021-10/+16
| | | | | | more work). llvm-svn: 28044
* Fix a latent bug that my spiller patch last week exposed: we were leavingChris Lattner2006-05-012-4/+7
| | | | | | | | | instructions in the virtregfolded map that were deleted. Because they were deleted, newly allocated instructions could end up at the same address, magically finding themselves in the map. The solution is to remove entries from the map when we delete the instructions. llvm-svn: 28041
* When promoting a load to a reg-reg copy, where the load was a previousChris Lattner2006-05-011-0/+1
| | | | | | | instruction folded with spill code, make sure the remove the load from the virt reg folded map. llvm-svn: 28040
* Remove previous patch, which wasn't quite right.Chris Lattner2006-05-013-24/+23
| | | | llvm-svn: 28039
* Dis-favor stores moreEvan Cheng2006-05-011-2/+2
| | | | llvm-svn: 28035
* Bottom up register-pressure reduction scheduler now pushes store operationsEvan Cheng2006-05-011-17/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | up the schedule. This helps code that looks like this: loads ... computations (first set) ... stores (first set) ... loads computations (seccond set) ... stores (seccond set) ... Without this change, the stores and computations are more likely to interleave: loads ... loads ... computations (first set) ... computations (second set) ... computations (first set) ... stores (first set) ... computations (second set) ... stores (stores set) ... This can increase the number of spills if we are unlucky. llvm-svn: 28033
* Didn't mean ScheduleDAGList.cpp to make the last checkin.Evan Cheng2006-05-011-33/+17
| | | | llvm-svn: 28030
* Remove temp. option -spiller-check-liveout, it didn't cause any failure nor ↵Evan Cheng2006-05-012-22/+34
| | | | | | performance regressions. llvm-svn: 28029
* Format #APP lines a bit nicerChris Lattner2006-05-011-2/+2
| | | | llvm-svn: 28026
* Local spiller kills a store if the folded restore is turned into a copy.Evan Cheng2006-04-303-10/+21
| | | | | | | | But this is incorrect if the spilled value live range extends beyond the current BB. It is currently controlled by a temporary option -spiller-check-liveout. llvm-svn: 28024
* Remove a bogus transformation. This fixes ↵Chris Lattner2006-04-281-7/+0
| | | | | | | | SingleSource/UnitTests/2006-01-23-InitializedBitField.c with some changes I have to the new CFE. llvm-svn: 28022
* Remove the temporary option: -no-isel-fold-inflightEvan Cheng2006-04-281-11/+0
| | | | llvm-svn: 28012
* TargetLowering::LowerArguments should return a VBIT_CONVERT ofEvan Cheng2006-04-281-16/+14
| | | | | | FORMAL_ARGUMENTS SDOperand in the return result vector. llvm-svn: 28009
* Mapping of physregs can make it so that the designated and input physregs areChris Lattner2006-04-281-0/+13
| | | | | | the same. In this case, don't emit a noop copy. llvm-svn: 28008
* Added a temporary option -no-isel-fold-inflight to control whether a "inflight"Evan Cheng2006-04-281-1/+12
| | | | | | node can be folded. llvm-svn: 28003
* When we have a two-address instruction where the input cannot be clobberedChris Lattner2006-04-281-26/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | and is already available, instead of falling back to emitting a load, fall back to emitting a reg-reg copy. This generates significantly better code for some SSE testcases, as SSE has lots of two-address instructions and none of them are read/modify/write. As one example, this change does: pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255 xorps %XMM2, %XMM5 cmpltps %XMM1, %XMM0 - movaps XMMWORD PTR [%ESP + 52], %XMM0 - movapd %XMM6, XMMWORD PTR [%ESP + 52] + movaps %XMM6, %XMM0 cmpltps %XMM6, XMMWORD PTR [%ESP + 68] movapd XMMWORD PTR [%ESP + 52], %XMM6 movaps %XMM6, %XMM0 cmpltps %XMM6, XMMWORD PTR [%ESP + 36] cmpltps %XMM3, %XMM0 - movaps XMMWORD PTR [%ESP + 20], %XMM0 - movapd %XMM7, XMMWORD PTR [%ESP + 20] + movaps %XMM7, %XMM0 cmpltps %XMM7, XMMWORD PTR [%ESP + 4] movapd XMMWORD PTR [%ESP + 20], %XMM7 cmpltps %XMM4, %XMM0 ... which is far better than a store followed by a load! llvm-svn: 28001
* Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector usesEvan Cheng2006-04-271-3/+16
| | | | | | (VAND, VADD, etc.). Legalizer will assert otherwise. llvm-svn: 27991
* Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll andChris Lattner2006-04-271-1/+29
| | | | | | PR748. llvm-svn: 27987
* Don't forget return void.Evan Cheng2006-04-251-0/+3
| | | | llvm-svn: 27974
* Fix the updating of the machine CFG when a PHI node was in a successor ofNate Begeman2006-04-231-5/+10
| | | | | | | the jump table's range check block. This re-enables 100% dense jump tables by default on PPC & x86 llvm-svn: 27952
* Code cleanup associated with jump tables, thanks to Chris for noticingNate Begeman2006-04-221-0/+8
| | | | | | these. llvm-svn: 27950
* Turn of jump tables for a bit, there are still some issues to work out withNate Begeman2006-04-221-1/+1
| | | | | | updating the machine CFG. llvm-svn: 27949
* JumpTable support! What this represents is working asm and jit support forNate Begeman2006-04-229-11/+281
| | | | | | | | x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. llvm-svn: 27947
* The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrapChris Lattner2006-04-211-2/+5
| | | | | | miscompares). Switch RISC targets to use the list-td scheduler, which isn't. llvm-svn: 27933
* Fix a couple more memory issuesChris Lattner2006-04-211-4/+4
| | | | llvm-svn: 27930
* Fix a really subtle and obnoxious memory bug that caused issues with anChris Lattner2006-04-201-11/+11
| | | | | | | | | llvm-gcc4 boostrap. Whenever a node is deleted by the dag combiner, it *must* be returned by the visit function, or the dag combiner will not know that the node has been processed (and will, e.g., send it to the target dag combine xforms). llvm-svn: 27922
* This field no longer existsChris Lattner2006-04-201-2/+0
| | | | llvm-svn: 27899
* Remove some of the obvious V9-specific cruftChris Lattner2006-04-201-101/+2
| | | | llvm-svn: 27893
* Turn a VAND into a VECTOR_SHUFFLE is applicable.Evan Cheng2006-04-201-1/+64
| | | | | | | | DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements, into a vector shuffle with a zero vector. It only does so when TLI tells it the xform is profitable. llvm-svn: 27874
* Implement folding of a bunch of binops with undefChris Lattner2006-04-201-0/+46
| | | | llvm-svn: 27863
* Simplify some codeChris Lattner2006-04-191-5/+1
| | | | llvm-svn: 27846
* Fix handling of calls in functions that use vectors. This fixes a crash onChris Lattner2006-04-171-13/+1
| | | | | | the code in GCC PR26546. llvm-svn: 27780
* Add a MachineInstr::eraseFromParent convenience method.Chris Lattner2006-04-171-0/+9
| | | | llvm-svn: 27775
* Codegen insertelement with constant insertion points as scalar_to_vectorChris Lattner2006-04-171-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and a shuffle. For this: void %test2(<4 x float>* %F, float %f) { %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2] %tmp3 = add <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1] %tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2 ; <<4 x float>> [#uses=2] %tmp6 = add <4 x float> %tmp2, %tmp2 ; <<4 x float>> [#uses=1] store <4 x float> %tmp6, <4 x float>* %F ret void } we now get this on X86 (which will get better): _test2: movl 4(%esp), %eax movaps (%eax), %xmm0 addps %xmm0, %xmm0 movaps %xmm0, %xmm1 shufps $3, %xmm1, %xmm1 movaps %xmm0, %xmm2 shufps $1, %xmm2, %xmm2 unpcklps %xmm1, %xmm2 movss 8(%esp), %xmm1 unpcklps %xmm1, %xmm0 unpcklps %xmm2, %xmm0 addps %xmm0, %xmm0 movaps %xmm0, (%eax) ret instead of: _test2: subl $28, %esp movl 32(%esp), %eax movaps (%eax), %xmm0 addps %xmm0, %xmm0 movaps %xmm0, (%esp) movss 36(%esp), %xmm0 movss %xmm0, 8(%esp) movaps (%esp), %xmm0 addps %xmm0, %xmm0 movaps %xmm0, (%eax) addl $28, %esp ret llvm-svn: 27765
* Add support for promoting stores from one legal type to another, allowing usChris Lattner2006-04-161-0/+8
| | | | | | to write one pattern for vector stores instead of 4. llvm-svn: 27730
* Make these predicates return true for bit_convert(buildvector)'s as well asChris Lattner2006-04-151-0/+8
| | | | | | buildvectors. llvm-svn: 27723
* Make this assertion betterChris Lattner2006-04-141-1/+1
| | | | llvm-svn: 27695
* Expand some code with temporary variables to rid ourselves of the warningReid Spencer2006-04-131-7/+21
| | | | | | about "dereferencing type-punned pointer will break strict-aliasing rules" llvm-svn: 27671
* Promote vector AND, OR, and XOREvan Cheng2006-04-121-0/+27
| | | | llvm-svn: 27632
* Vector type promotion for ISD::LOAD and ISD::SELECTEvan Cheng2006-04-121-9/+23
| | | | llvm-svn: 27606
* Implement support for the formal_arguments node. To get this, targets ↵Chris Lattner2006-04-123-3/+128
| | | | | | shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload llvm-svn: 27604
* Don't memoize vloads in the load map! Don't memoize them anywhere here, letChris Lattner2006-04-121-2/+0
| | | | | | getNode do it. This fixes CodeGen/Generic/2006-04-11-vecload.ll llvm-svn: 27602
* Only get Tmp2 for cases where number of operands is > 1. Fixed return void.Evan Cheng2006-04-111-1/+1
| | | | llvm-svn: 27586
* add some todosChris Lattner2006-04-111-0/+8
| | | | llvm-svn: 27580
* Add basic support for legalizing returns of vectorsChris Lattner2006-04-111-9/+36
| | | | llvm-svn: 27578
* Use existing information.Jim Laskey2006-04-101-3/+14
| | | | llvm-svn: 27574
* Missing breakEvan Cheng2006-04-101-0/+1
| | | | llvm-svn: 27559
* Add code generator support for VSELECTChris Lattner2006-04-083-10/+22
| | | | llvm-svn: 27542
* Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patternsChris Lattner2006-04-082-2/+50
| | | | | | to match again :) llvm-svn: 27533
* Codegen shufflevector as VVECTOR_SHUFFLEChris Lattner2006-04-082-2/+25
| | | | llvm-svn: 27529
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