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authorChris Lattner <sabre@nondot.org>2006-04-28 23:33:20 +0000
committerChris Lattner <sabre@nondot.org>2006-04-28 23:33:20 +0000
commit2b48a9441306184c995bab10ce7b7e3375b47cb4 (patch)
tree763cbb46444be7a4b9351950bd821ff778289f19 /llvm/lib/CodeGen
parentd369603df9f73bfbb1c504f946cf0018f813b801 (diff)
downloadbcm5719-llvm-2b48a9441306184c995bab10ce7b7e3375b47cb4.tar.gz
bcm5719-llvm-2b48a9441306184c995bab10ce7b7e3375b47cb4.zip
Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
with some changes I have to the new CFE. llvm-svn: 28022
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp7
1 files changed, 0 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e9b30cb38bd..ac70150f8e0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1899,13 +1899,6 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
return DAG.getZeroExtendInReg(N0, EVT);
- // fold (sext_in_reg (srl x)) -> sra x
- if (N0.getOpcode() == ISD::SRL &&
- N0.getOperand(1).getOpcode() == ISD::Constant &&
- cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
- return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
- N0.getOperand(1));
- }
// fold (sext_inreg (extload x)) -> (sextload x)
if (N0.getOpcode() == ISD::EXTLOAD &&
EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
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