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* sink management of DwarfWriter & MachineModuleInfo into the AsmPrinter base ↵Chris Lattner2009-06-241-10/+10
| | | | | | class. llvm-svn: 74101
* sink dwarf finalization out of each target into AsmPrinter::doFinalizationChris Lattner2009-06-241-0/+4
| | | | llvm-svn: 74097
* eliminate the ExtWeakSymbols set from AsmPrinter. This eliminatesChris Lattner2009-06-241-8/+21
| | | | | | | a bunch of code from all the targets, and eliminates nondeterministic ordering of directives being emitted in the output. llvm-svn: 74096
* Rearrange some stuff in MachineOperand and add a new TargetFlags field.Chris Lattner2009-06-241-25/+29
| | | | llvm-svn: 74087
* Get rid of the global CFGOnly flag by threading a ShortNames parameters ↵Owen Anderson2009-06-243-20/+23
| | | | | | | | through the GraphViz rendering code. Update other uses in the codebase for this change. llvm-svn: 74084
* Rewrite 73900 per Duncan's suggestion.Dale Johannesen2009-06-241-19/+9
| | | | llvm-svn: 74082
* remove dead makefile flags.Chris Lattner2009-06-242-4/+0
| | | | llvm-svn: 74065
* Fixed a bug in LiveInterval scaling (failure to scale VNI defs correctly), ↵Lang Hames2009-06-242-6/+2
| | | | | | removed old TODO comments. llvm-svn: 74054
* Fix support for inline asm input / output operand tying when operand spans ↵Evan Cheng2009-06-241-11/+23
| | | | | | across multiple registers (e.g. two i64 operands in 32-bit mode). llvm-svn: 74053
* Use a default alignment for data and bss sections.Bruno Cardoso Lopes2009-06-232-19/+25
| | | | | | | | Only pad when the section size > 0 and move the code that deals with globals initializers to a place we know for sure the global is initialized. llvm-svn: 73944
* Fix memcpy expansion so it won't generate invalidDale Johannesen2009-06-221-6/+25
| | | | | | | types for the target (I think). This was breaking the PPC32 calling sequence. llvm-svn: 73900
* Fix another register coalescer crash: forgot to check if the instruction ↵Evan Cheng2009-06-221-3/+7
| | | | | | being updated has already been coalesced. llvm-svn: 73898
* Use different functions to emit the string and symbol tables.Bruno Cardoso Lopes2009-06-222-7/+17
| | | | llvm-svn: 73895
* Add more methods to gather target specific elf stuffBruno Cardoso Lopes2009-06-224-154/+312
| | | | | | | | Support for .text relocations, implementing TargetELFWriter overloaded methods for x86/x86_64. Use a map to track global values to their symbol table indexes Code cleanup and small fixes llvm-svn: 73894
* Fix PR4419: handle defs of partial uses.Evan Cheng2009-06-201-7/+6
| | | | llvm-svn: 73816
* mv CodeGen/DebugLoc.h Support/DebugLoc.hDevang Patel2009-06-191-1/+0
| | | | llvm-svn: 73786
* Move up dwarf writer initialization in common AsmPrinter class.Devang Patel2009-06-191-3/+11
| | | | llvm-svn: 73784
* Minor cleanup; fixes review comments for a previous patch. Sorry for Eli Friedman2009-06-191-4/+3
| | | | | | taking so long to get to this! llvm-svn: 73757
* More VNInfo tweaking, plus a little progress on intra-block splitting.Lang Hames2009-06-193-25/+84
| | | | llvm-svn: 73750
* move mangler quote handling from asm printers to TargetAsmInfo.Chris Lattner2009-06-181-0/+3
| | | | llvm-svn: 73738
* simplify macro debug info directive handling.Chris Lattner2009-06-181-4/+4
| | | | llvm-svn: 73736
* Improved PHI def marking, replaced some gotos with breaks.Lang Hames2009-06-181-5/+7
| | | | llvm-svn: 73727
* On Darwin, ams printer should output a second label before a jump table so ↵Evan Cheng2009-06-181-3/+7
| | | | | | the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body. llvm-svn: 73720
* - Update register allocation hint after coalescing. This is done by the ↵Evan Cheng2009-06-182-2/+11
| | | | | | | | | target since the hint is target dependent. This is important for ARM register pair hints. - Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping. - More fixes to get ARM load / store double word working. llvm-svn: 73671
* VNInfo cleanup.Lang Hames2009-06-179-125/+151
| | | | llvm-svn: 73634
* Fixed names of libcalls checked in r73480.Sanjiv Gupta2009-06-161-8/+4
| | | | llvm-svn: 73483
* Added required libcalls for PIC16 (mostly floating points to integer casting ↵Sanjiv Gupta2009-06-161-0/+16
| | | | | | operations). llvm-svn: 73480
* Rename RemoveCopiesFromValNo to TurnCopiesFromValNoToImpDefs.Evan Cheng2009-06-162-10/+10
| | | | llvm-svn: 73479
* If a val# is defined by an implicit_def and it is being removed, all of the ↵Evan Cheng2009-06-161-20/+27
| | | | | | | | copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead. TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block. llvm-svn: 73478
* Add some generic expansion logic for SMULO and UMULO. Fixes UMULO Eli Friedman2009-06-161-0/+47
| | | | | | | | support for x86, and UMULO/SMULO for many architectures, including PPC (PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's not bad. llvm-svn: 73477
* Fix typos.Bill Wendling2009-06-161-2/+2
| | | | llvm-svn: 73464
* Use MainCU if it is available.Devang Patel2009-06-161-2/+3
| | | | llvm-svn: 73457
* Owen Anderson 2009-06-15: Use a SmallPtrSet here, for speed and to match ↵Owen Anderson2009-06-151-5/+14
| | | | | | | | df_iterator. Owen Anderson 2009-06-15: Remember to clear out our maps to prevent crashing. llvm-svn: 73438
* Change this from an assert to a cerr+exit, since it's diagnosing anDan Gohman2009-06-151-2/+6
| | | | | | unsupported inline asm construct, rather than verifying a code invariant. llvm-svn: 73435
* Gracefully handle imbalanced inline function begin and end markers.Devang Patel2009-06-152-2/+9
| | | | llvm-svn: 73426
* ifcvt should ignore cfg where true and false successors are the same.Evan Cheng2009-06-151-1/+12
| | | | llvm-svn: 73423
* CheckTailCallReturnConstraints is missing a check on theArnold Schwaighofer2009-06-151-1/+5
| | | | | | | | | incomming chain of the RETURN node. The incomming chain must be the outgoing chain of the CALL node. This causes the backend to identify tail calls that are not tail calls. This patch fixes this. llvm-svn: 73387
* Part 1.Evan Cheng2009-06-155-86/+39
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Fix old-style type names in comments.Dan Gohman2009-06-141-1/+1
| | | | llvm-svn: 73362
* Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng2009-06-148-37/+142
| | | | | | MachineRegisterInfo. This allows more passes to set them. llvm-svn: 73346
* Introduce new BinaryObject (blob) class, ELF Writer modified to use it. ↵Bruno Cardoso Lopes2009-06-144-257/+182
| | | | | | BinaryObject.h by Aaron Gray llvm-svn: 73333
* Add a ARM specific pre-allocation pass that re-schedule loads / stores fromEvan Cheng2009-06-131-1/+1
| | | | | | | | | | | consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. llvm-svn: 73291
* llvm.dbg.region.end() intrinsic is not required to be in _last_ basic block ↵Devang Patel2009-06-131-1/+5
| | | | | | | | in a function. If that happens then any basic block that follows (lexically) the block with regin.end will not have scope info available. LexicalScopeStack relies on processing basic block in CFG order, but this processing order is not guaranteed. Things get complicated when the optimizer gets a chance to optimizer IR with dbg intrinsics. Apply defensive patch to preserve at least one lexical scope till the end of function. llvm-svn: 73282
* Improve style.Owen Anderson2009-06-121-16/+16
| | | | llvm-svn: 73258
* This is supposed to be a preorder numbering of the dominator tree, not the CFG.Owen Anderson2009-06-121-4/+5
| | | | llvm-svn: 73257
* Now with less iterator invalidation, and other forms of crashing!Owen Anderson2009-06-121-3/+6
| | | | llvm-svn: 73256
* If killed register is defined by implicit_def, do not clear it since it's ↵Evan Cheng2009-06-121-5/+12
| | | | | | live range may overlap another def of same register. llvm-svn: 73255
* Clear AbstractInstanceRootMap at the end of the function.Devang Patel2009-06-121-0/+1
| | | | llvm-svn: 73244
* Support for ELF VisibilityBruno Cardoso Lopes2009-06-114-93/+295
| | | | | | | | Emission for globals, using the correct data sections Function alignment can be computed for each target using TargetELFWriterInfo Some small fixes llvm-svn: 73201
* CMake: Updated list of files on lib/CodeGen/CMakeLists.txt.Oscar Fuentes2009-06-101-0/+1
| | | | llvm-svn: 73174
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