| Commit message (Collapse) | Author | Age | Files | Lines |
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class.
llvm-svn: 74101
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llvm-svn: 74097
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a bunch of code from all the targets, and eliminates nondeterministic
ordering of directives being emitted in the output.
llvm-svn: 74096
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llvm-svn: 74087
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through the GraphViz rendering code.
Update other uses in the codebase for this change.
llvm-svn: 74084
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llvm-svn: 74082
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llvm-svn: 74065
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removed old TODO comments.
llvm-svn: 74054
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across multiple registers (e.g. two i64 operands in 32-bit mode).
llvm-svn: 74053
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Only pad when the section size > 0 and move the code that deals
with globals initializers to a place we know for sure the global
is initialized.
llvm-svn: 73944
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types for the target (I think). This was breaking
the PPC32 calling sequence.
llvm-svn: 73900
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being updated has already been coalesced.
llvm-svn: 73898
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llvm-svn: 73895
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Support for .text relocations, implementing TargetELFWriter overloaded methods for x86/x86_64.
Use a map to track global values to their symbol table indexes
Code cleanup and small fixes
llvm-svn: 73894
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llvm-svn: 73816
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llvm-svn: 73786
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llvm-svn: 73784
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taking so long to get to this!
llvm-svn: 73757
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llvm-svn: 73750
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llvm-svn: 73738
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llvm-svn: 73736
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llvm-svn: 73727
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the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
llvm-svn: 73720
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target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.
llvm-svn: 73671
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llvm-svn: 73634
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llvm-svn: 73483
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operations).
llvm-svn: 73480
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llvm-svn: 73479
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copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead.
TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block.
llvm-svn: 73478
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support for x86, and UMULO/SMULO for many architectures, including PPC
(PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's
not bad.
llvm-svn: 73477
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llvm-svn: 73464
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llvm-svn: 73457
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df_iterator.
Owen Anderson 2009-06-15: Remember to clear out our maps to prevent crashing.
llvm-svn: 73438
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unsupported inline asm construct, rather than verifying a code invariant.
llvm-svn: 73435
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llvm-svn: 73426
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llvm-svn: 73423
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incomming chain of the RETURN node. The incomming chain must
be the outgoing chain of the CALL node. This causes the
backend to identify tail calls that are not tail calls. This
patch fixes this.
llvm-svn: 73387
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- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
llvm-svn: 73381
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llvm-svn: 73362
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MachineRegisterInfo. This allows more passes to set them.
llvm-svn: 73346
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BinaryObject.h by Aaron Gray
llvm-svn: 73333
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consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.
This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.
llvm-svn: 73291
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in a function. If that happens then any basic block that follows (lexically) the block with regin.end will not have scope info available. LexicalScopeStack relies on processing basic block in CFG order, but this processing order is not guaranteed. Things get complicated when the optimizer gets a chance to optimizer IR with dbg intrinsics.
Apply defensive patch to preserve at least one lexical scope till the end of function.
llvm-svn: 73282
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llvm-svn: 73258
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llvm-svn: 73257
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llvm-svn: 73256
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live range may overlap another def of same register.
llvm-svn: 73255
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llvm-svn: 73244
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Emission for globals, using the correct data sections
Function alignment can be computed for each target using TargetELFWriterInfo
Some small fixes
llvm-svn: 73201
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llvm-svn: 73174
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