| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 78363
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llvm-svn: 78362
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llvm-svn: 78360
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stuff as it was only meant for debugging the solver.
llvm-svn: 78359
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based solver, but I'll be working to improve that. The PBQP allocator has been updated to use the new solver.
llvm-svn: 78354
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produced a CFG it wasn't prepared for.
llvm-svn: 78351
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llvm-svn: 78350
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If we need it one day, there is nothing wrong with putting it back in.
llvm-svn: 78337
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- start support for new PEI w/reg alloc, allow running RS from emit{Pro,Epi}logue() target hooks.
- fix minor issue with recursion detection.
llvm-svn: 78318
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and LowerReturn, to verify that the targets' hooks have respected some
of their postconditions.
llvm-svn: 78312
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types don't have any return values, from CodeGen's perspective.
This fixes PR4688.
llvm-svn: 78311
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and high-bits values in ways that weren't correct for integer
types wider than 64 bits. This fixes a miscompile in
PPMacroExpansion.cpp in clang on x86-64.
llvm-svn: 78295
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contexts through a number of APIs.
llvm-svn: 78258
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and eliminate complexity. Yay!
llvm-svn: 78243
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llvm-svn: 78242
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llvm-svn: 78202
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llvm-svn: 78179
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After coalescing reg1027's def and kill are both at the same point:
%reg1027,0.000000e+00 = [56,814:0) 0@70-(814)
bb5:
60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>
Do not remove the kill marker on t2LDRi12.
llvm-svn: 78178
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llvm-svn: 78177
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a dirty hack and isn't need anymore since the last x86 code emitter patch)
- Add a target-dependent modifier to addend calculation
- Use R_X86_64_32S relocation for X86::reloc_absolute_word_sext
- Use getELFSectionFlags whenever possible
- fix getTextSection to use TLOF and emit the right text section
- Handle global emission for static ctors, dtors and Type::PointerTyID
- Some minor fixes
llvm-svn: 78176
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llvm-svn: 78154
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llvm-svn: 78151
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llvm-svn: 78145
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llvm-svn: 78144
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Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
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copy.
llvm-svn: 78141
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llvm-svn: 78139
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This fixes PR4528.
llvm-svn: 78107
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scavenger.
Imp-def is *not* allowed to redefine a live register.
Imp-use is *not* allowed to use a dead register.
llvm-svn: 78106
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the masm backend. If anyone cares about masm in the future,
we'll have semantic sections it can hang off of.
llvm-svn: 78096
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For an undef operand, MO.getReg() is meaningless and we should not use it.
Undef operands should be skipped entirely.
llvm-svn: 78095
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of registers.
When LowerExtract eliminates an EXTRACT_SUBREG with a kill flag, it moves the
kill flag to the place where the sub-register is killed. This can accidentally
overlap with the use of a sibling sub-register, and we have trouble.
In the test case we have this code:
Live Ins: %R0 %R1 %R2
%R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
%R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0]
%R1L<def> = EXTRACT_SUBREG %R1<kill>, 1
%R0L<def> = EXTRACT_SUBREG %R0<kill>, 1
%R0H<def> = ADD16 %R2H<kill>, %R2L<kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def>
subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
subreg: eliminated!
subreg: killed here: %R0H<def> = ADD16 %R2H, %R2L, %R2<imp-use,kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def>
The kill flag on %R2 is moved to the last instruction, and the live range overlaps with the definition of %R2H:
*** Bad machine code: Redefining a live physical register ***
- function: f
- basic block: 0x18358c0 (#0)
- instruction: %R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0]
Register R2H was defined but already live.
The fix is to replace EXTRACT_SUBREG with IMPLICIT_DEF instead of eliminating
it completely:
subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
subreg: replace by: %R2L<def> = IMPLICIT_DEF %R2<kill>
Note that these IMPLICIT_DEF instructions survive to the asm output. It is
necessary to fix the stack-color-with-reg test case because of that.
llvm-svn: 78093
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Implicit operands no longer get a free pass: Imp-use requires a live register
and imp-def requires a dead register.
There is also no special rule allowing redefinition of a sub-register when the
super-register is live. The super register must have imp-kill+imp-def operands
instead.
llvm-svn: 78090
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killed by another operand.
There is probably a better fix. Either 1) scavenger can look at other operands, or
2) livevariables can be smarter about kill markers. Patches welcome.
llvm-svn: 78072
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TLI.computeMaskedBitsForTargetNode from ComputeMaskedBits, since
the former may call back into the latter. This fixes a major
compile time problem on a testcase that happnened to hit this
in a particularly bad way, PR4643.
llvm-svn: 78023
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llvm-svn: 78020
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private,
eliminate IsInTextSection.
llvm-svn: 78017
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llvm-svn: 78015
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and others.
llvm-svn: 78003
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When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG
instriction because it is an identity copy, make sure that the same registers
are alive before and after the elimination.
When the super-register is marked <undef> this requires inserting an
IMPLICIT_DEF instruction to make sure the super register is live.
Fix a related bug where a kill flag on the inserted sub-register was not transferred properly.
Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid.
llvm-svn: 77989
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llvm-svn: 77984
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llvm-svn: 77982
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llvm-svn: 77976
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trying the standard stuff.
llvm-svn: 77974
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like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".
llvm-svn: 77971
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non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy.
llvm-svn: 77967
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llvm-svn: 77931
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not been spilled.
llvm-svn: 77912
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instruction.
llvm-svn: 77906
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Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier.
Allow redefinition of a sub-register of a live register.
llvm-svn: 77904
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