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authorEvan Cheng <evan.cheng@apple.com>2009-08-05 01:29:24 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-08-05 01:29:24 +0000
commitcdb125ce66bc3cc911abcf132239b01cdd2ca442 (patch)
tree7b89323ce9facbf7abd065490e9e91707007a87a /llvm/lib/CodeGen
parent1a90e384712164b42a676abe254dea1ef4fc8c3c (diff)
downloadbcm5719-llvm-cdb125ce66bc3cc911abcf132239b01cdd2ca442.tar.gz
bcm5719-llvm-cdb125ce66bc3cc911abcf132239b01cdd2ca442.zip
If the insert_subreg source is <undef>, insert an implicit_def instead of a copy.
llvm-svn: 78141
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/LowerSubregs.cpp10
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/LowerSubregs.cpp b/llvm/lib/CodeGen/LowerSubregs.cpp
index 9c23a5ac155..e9e60a00f0e 100644
--- a/llvm/lib/CodeGen/LowerSubregs.cpp
+++ b/llvm/lib/CodeGen/LowerSubregs.cpp
@@ -254,7 +254,13 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
// Insert sub-register copy
const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
- TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
+ if (MI->getOperand(2).isUndef())
+ // If the source register being inserted is undef, then this becomes an
+ // implicit_def.
+ BuildMI(*MBB, MI, MI->getDebugLoc(),
+ TII.get(TargetInstrInfo::IMPLICIT_DEF), DstSubReg);
+ else
+ TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
MachineBasicBlock::iterator CopyMI = MI;
--CopyMI;
@@ -270,7 +276,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
}
// Make sure the inserted register gets killed
- if (MI->getOperand(2).isKill())
+ if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
TransferKillFlag(MI, InsReg, TRI);
}
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