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* In the below scenario, we must be able to skip the a DBG_VALUE instruction andSumanth Gundapaneni2017-01-091-3/+8
| | | | | | | | | | | | | | | remove the dead store. %vreg0<def> = L2_loadri_io <fi#15>, 0; mem:LD4[%dataF](align=4) DBG_VALUE %vreg0, %noreg, !"dataF", <!184>; IntRegs:%vreg0 S2_storeri_io <fi#15>, 0, %vreg0; mem:ST4[%dataF] In reality, this kind of stores are eliminated before Stack Slot Coloring pass, possibly in instruction lowering Differential Revision: https://reviews.llvm.org/D26616 llvm-svn: 291455
* [SelectionDAG] Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486.Bjorn Pettersson2017-01-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Originally i64 = umax t8, Constant:i64<4> was expanded into i32,i32 = umax Constant:i32<0>, Constant:i32<0> i32,i32 = umax t7, Constant:i32<4> Now instead the two produced umax:es return i32 instead of i32, i32. Thanks to Jan Vesely for help with the test case. Patch by mikael.holmen at ericsson.com Reviewers: bogner, jvesely, tstellarAMD, arsenm Subscribers: test, wdng, RKSimon, arsenm, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D28135 llvm-svn: 291441
* [globalisel] Stop requiring -debug/-debug-only=registerbankinfo for assertions.Daniel Sanders2017-01-061-6/+7
| | | | | | | | | | | | | | | | | | | | | Summary: I've noticed that these assertions don't trigger when the condition is false. The problem is that the DEBUG(x) macro only executes x when the pass is emitting debug output via the -debug and -debug-only=registerbankinfo command line arguments. Debug builds should always execute the assertions so use '#ifndef NDEBUG' instead. Also removed an assertion that is only true the first time it's tested. <Target>RegisterBankInfo's constructor will re-use register banks causing them to be valid on subsequent tests. That assertion will fail on the first test too in the near future. Reviewers: t.p.northover, ab, rovka, qcolombet Subscribers: dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D28358 llvm-svn: 291235
* [SelectionDAG] Rework lowerRangeToAssertZExtDavid Majnemer2017-01-061-6/+11
| | | | | | Utilize ConstantRange to make it easier to interpret range metadata. llvm-svn: 291211
* [SelectionDAG] Correctly transform range metadata to AssertZExtDavid Majnemer2017-01-061-1/+1
| | | | | | | | We used the logBase2 of the high instead of the ceilLogBase2 resulting in the wrong result for certain values. For example, it resulted in an i1 AssertZExt when the exclusive portion of the range was 3. llvm-svn: 291196
* PR 31534: When emitting both DWARF unwind tables and debug information,Joerg Sonnenberger2017-01-053-3/+26
| | | | | | | do not use .cfi_sections. This requires checking if any non-declaration function in the module needs an unwind table. llvm-svn: 291172
* CodeGen: Assert that liveness is up to date when reading block live-ins.Matthias Braun2017-01-055-35/+47
| | | | | | | | | | | | | | | | | Add an assert that checks whether liveins are up to date before they are used. - Do not print liveins into .mir files anymore in situations where they are out of date anyway. - The assert in the RegisterScavenger is superseded by the new one in livein_begin(). - Skip parts of the liveness updating logic in IfConversion.cpp when liveness isn't tracked anymore (just enough to avoid hitting the new assert()). Differential Revision: https://reviews.llvm.org/D27562 llvm-svn: 291169
* [GlobalISel] Add support for address-taken basic blocksKristof Beyls2017-01-051-1/+4
| | | | | | | | | | | | | | | | | To make this work, pointers from the MachineBasicBlock to the LLVM-IR-level basic blocks need to be initialized, as the AsmPrinter uses this link to be able to print out labels for the basic blocks that are address-taken. Most of the changes in this commit are about adapting existing tests to include the basic block name that is now printed out in the MIR format, now that the name becomes available as the link to the LLVM-IR basic block is initialized. The relevant test change for the functionality added in this patch are the added "(address-taken)" strings in test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll. Differential Revision: https://reviews.llvm.org/D28123 llvm-svn: 291105
* [GlobalISel] Add support for switch statementsKristof Beyls2017-01-051-0/+39
| | | | | | | | | | This commit does this using a trivial chain of conditional branches. In the future, we probably want to reuse the optimized switch lowering used in SelectionDAG. Differential Revision: https://reviews.llvm.org/D28176 llvm-svn: 291099
* MC: support passing search paths to the IASSaleem Abdulrasool2017-01-051-0/+2
| | | | | | | This is needed to support inclusion in inline assembly via the `.include` directive. llvm-svn: 291085
* [Legalizer] Fix fp-to-uint to fp-tosint promotion assertion.Tim Shen2017-01-041-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When promoting fp-to-uint16 to fp-to-sint32, the result is actually zero extended. For example, given double 65534.0, without legalization: fp-to-uint16: 65534.0 -> 0xfffe With the legalization: fp-to-sint32: 65534.0 -> 0x0000fffe Without this patch, legalization wrongly emits a signed extend assertion, which is consumed by later icmp instruction, and cause miscompile. Note that the floating point value must be in [0, 65535), otherwise the behavior is undefined. This patch reverts r279223 behavior and adds more tests and documentations. In PR29041's context, James Molloy mentioned that: We don't need to mask because conversion from float->uint8_t is undefined if the integer part of the float value is not representable in uint8_t. Therefore we can assume this doesn't happen! which is totally true and good, because fptoui is documented clearly to have undefined behavior when overflow/underflow happens. We should take the advantage of this behavior so that we can save unnecessary mask instructions. Reviewers: jmolloy, nadav, echristo, kbarton Subscribers: mehdi_amini, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D28284 llvm-svn: 291015
* The patch fixes (base, index, offset) match.Evgeny Stupachenko2017-01-041-9/+9
| | | | | | | | | | | | | | | Summary: Instead of matching: (a + i) + 1 -> (a + i, undef, 1) Now it matches: (a + i) + 1 -> (a, i, 1) Reviewers: rengolin Differential Revision: http://reviews.llvm.org/D26367 From: Evgeny Stupachenko <evstupac@gmail.com> llvm-svn: 291012
* Fix for InlineSpiller accessing not updated dom tree base information.Bjorn Pettersson2017-01-041-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The InlineSpiller was accessing the DominatorTreeBase directly through the public data member DT in the MachineDominatorTree. This is not a good idea as the "cached" information in SplitCriticalEdges is not applied before the access. The DominatorTreeBase must be accessed through the member function getBase() in MachineDominatorTree. The fault was introduced in r266162. I think the public data member DT in the MachineDominatorTree should have been made private in the original code (r215576) that introduced the concept of lazily updating the MachineDominatorTree information from MachineBasicBlock::SplitCriticalEdge(). Patch by Karl-Johan Karlsson <karl-johan.karlsson@ericsson.com> Reviewers: wmi, qcolombet Subscribers: llvm-commits, bjope, uabelho Differential Revision: https://reviews.llvm.org/D27983 llvm-svn: 290950
* [CodeGen] Further simplify returned call operand logic. NFC.Ahmed Bougacha2017-01-031-8/+2
| | | | | | As Pete points out in r290905, CallSite lets us avoid duplicating this! llvm-svn: 290909
* [CodeGen] Simplify logic that looks for returned call operands. NFC-ish.Ahmed Bougacha2017-01-031-22/+10
| | | | | | | | | | | | | | | Use getReturnedArgOperand() instead of rolling our own. Note that it's equivalent because there can only be one 'returned' operand. The existing code was also incorrect: there already was awkward logic to ignore callee/EH blocks, but operands can now also be operand bundles, in which case we'll look for non-existent parameter attributes. Unfortunately, this isn't observable in-tree, as it only crashes when exercising the regular call lowering logic with operand bundles. Still, this is a nice small cleanup anyway. llvm-svn: 290905
* [XRay] Merge instrumentation point table emission code into AsmPrinter.Dean Michael Berris2017-01-031-0/+57
| | | | | | | | | | | | | | | | | | Summary: No need to have this per-architecture. While there, unify 32-bit ARM's behaviour with what changed elsewhere and start function names lowercase as per the coding standards. Individual entry emission code goes to the entry's own class. Fully tested on amd64, cross-builds on both ARMs and PowerPC. Reviewers: dberris Subscribers: aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D28209 llvm-svn: 290858
* Emit .cfi_sections before the first .cfi_startprocJoerg Sonnenberger2017-01-023-19/+17
| | | | | | | | | | | GNU as rejects input where .cfi_sections is used after .cfi_startproc, if the new section differs from the old. Adjust our output to always emit .cfi_sections before the first .cfi_startproc to minimize necessary code. Differential Revision: https://reviews.llvm.org/D28011 llvm-svn: 290817
* Reapply "[CodeGen] Fix invalid DWARF info on Win64"Keno Fischer2017-01-024-6/+9
| | | | | | | This reapplies rL289013 (reverted in rL289014) with the fixes identified in D21731. Should hopefully pass the buildbots this time. llvm-svn: 290809
* [selectiondag] Check PromotedFloats map during expansive checks.Florian Hahn2017-01-011-0/+4
| | | | | | | | | | | | | | | Summary: `PromotedFloats` needs to be checked in `DAGTypeLegalizer::PerformExpensiveChecks`. This patch fixes a few type legalization failures with expansive checks for ARM fp16 tests. Reviewers: baldrick, bogner, arsenm Subscribers: arsenm, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D28187 llvm-svn: 290796
* Simplify FunctionLoweringInfo.cpp with range for loopsReid Kleckner2016-12-301-40/+31
| | | | | | | I'm preparing to add some pattern matching code here, so simplify the code before I do. NFC llvm-svn: 290731
* Revert "[COFF] Use 32-bit jump table entries in .rdata for Win64"Reid Kleckner2016-12-291-7/+0
| | | | | | | | This reverts commit r290694. It broke sanitizer tests on Win64. I'll probably bring this back, but the jump tables will just live in .text like they do for MSVC. llvm-svn: 290714
* Introduce element-wise atomic memcpy intrinsicIgor Laevsky2016-12-292-0/+68
| | | | | | | | | | This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
* [COFF] Use 32-bit jump table entries in .rdata for Win64Reid Kleckner2016-12-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: We were already using 32-bit jump table entries, but this was a consequence of the default PIC model on Win64, and not an intentional design decision. This patch ensures that we always use 32-bit label difference jump table entries on Win64 regardless of the PIC model. This is a good idea because it saves executable size and object file size. Moving the jump tables to .rdata cleans up the disassembled object code and reduces the available ROP targets, but it requires adding one more RIP-relative lea to the code. COFF doesn't have relocations to express the difference between two arbitrary symbols, so we can't use the jump table label in the label difference like we do elsewhere. Fixes PR31488 Reviewers: majnemer, compnerd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28141 llvm-svn: 290694
* [WinEH] Don't assume endFunction is called while in .textReid Kleckner2016-12-282-10/+11
| | | | | | | | | | | | Jump table emission can switch to .rdata before WinException::endFunction gets called. Just remember the appropriate text section we started in and reset back to it when we end the function. We were already switching sections back from .xdata anyway. Fixes the first problem in PR31488, so that now COFF switch tables can live in .rdata if we want them to. llvm-svn: 290678
* [SelectionDAG] Early out from computeKnownBits when we know we will have no ↵Simon Pilgrim2016-12-241-8/+26
| | | | | | | | common bits. Avoid extra (recursive) calls to computeKnownBits if we already know that there are no common known bits. llvm-svn: 290490
* Make the canonicalisation on shifts benifit to more case.Zijiao Ma2016-12-231-9/+13
| | | | | | | | | | | 1.Fix pessimized case in FIXME. 2.Add tests for it. 3.The canonicalisation on shifts results in different sequence for tests of machine-licm.Correct some check lines. Differential Revision: https://reviews.llvm.org/D27916 llvm-svn: 290410
* NFC code motion in ImplicitNullChecksSanjoy Das2016-12-231-96/+106
| | | | | | Extract out two large lambdas into top level member functions. llvm-svn: 290395
* Reimplement depedency tracking in the ImplicitNullChecks passSanjoy Das2016-12-231-201/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change rewrites a core component in the ImplicitNullChecks pass for greater simplicity since the original design was over-complicated for no good reason. Please review this as essentially a new pass. The change is almost NFC and I've added a test case for a scenario that this new code handles that wasn't handled earlier. The implicit null check pass, at its core, is a code hoisting transform. It differs from "normal" code transforms in that it speculates potentially faulting instructions (by design), but a lot of the usual hazard detection logic (register read-after-write etc.) still applies. We previously detected hazards by keeping track of registers defined and used by machine instructions over an instruction range, but that was unwieldy and did not actually confer any performance benefits. The intent was to have linear time complexity over the number of machine instructions considered, but it ended up being N^2 is practice. This new version is more obviously O(N^2) (with N capped to 8 by default) in hazard detection. It does not attempt to be clever in tracking register uses or defs (the previous cleverness here was a source of bugs). Once this is checked in, I'll extract out the `IsSuitableMemoryOp` and `CanHoistLoadInst` lambda into member functions (they're too complicated to be inline lambdas) and do some other related NFC cleanups. Reviewers: reames, anna, atrick Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D27592 llvm-svn: 290394
* [GlobalISel] More fix for the size vs. type typo. NFC.Quentin Colombet2016-12-222-4/+4
| | | | | | I missed those in my previous commit (r290378). llvm-svn: 290387
* [MachineVerifier] Check that even generic vregs comply to regclass constraints.Quentin Colombet2016-12-221-0/+15
| | | | | | | | | We used to not check generic vregs, but that is actually a mistake given nothing in the GlobalISel pipeline is going to fix the constraints on target specific instructions. Therefore, the target has to have them right from the start. llvm-svn: 290380
* [MIRParser] Fix a typo in comment and error message.Quentin Colombet2016-12-221-2/+2
| | | | | | We have long switched from size to type. llvm-svn: 290378
* [MIRParser] Non-generic virtual register may have a type.Quentin Colombet2016-12-221-3/+0
| | | | | | | | When generic virtual registers get constrained, because of a use on a target specific operation for instance, we end up with regular virtual registers with a type and that's perfectly fine. llvm-svn: 290376
* [RegisterBankInfo] Allow to set a register class when nothing else is setQuentin Colombet2016-12-221-3/+2
| | | | | | | | This is going to be needed to be able to constraint register class on target specific instruction while the RegBankSelect pass did not run yet. llvm-svn: 290375
* [GlobalISel] Refactor the logic to constraint registers.Quentin Colombet2016-12-223-12/+53
| | | | | | | | Move the logic to constraint register from InstructionSelector to a utility function. It will be required by other passes in the GlobalISel pipeline. llvm-svn: 290374
* Redo store splitting in CodeGenPrepare.Wei Mi2016-12-221-0/+117
| | | | | | | | | | | | This is a succeeding patch of https://reviews.llvm.org/D22840 to address the issue when a value to be merged into an int64 pair is in a different BB. Redoing the store splitting in CodeGenPrepare so we can match the pattern across multiple BBs and move some instructions into the same BB. We still keep the code in dag combine so that we can catch cases that show up after DAG combining runs. Differential Revision: https://reviews.llvm.org/D25914 llvm-svn: 290365
* Change the interface of TLI.isMultiStoresCheaperThanBitsMerge.Wei Mi2016-12-221-2/+9
| | | | | | | | | This is for splitMergedValStore in DAG Combine to share the target query interface with similar logic in CodeGenPrepare. Differential Revision: https://reviews.llvm.org/D24707 llvm-svn: 290363
* Add the DAG mutation interface to the software pipelinerKrzysztof Parzyszek2016-12-221-1/+18
| | | | llvm-svn: 290360
* Fix two bugs in the pipeliner in renaming phis in the prolog and epilogKrzysztof Parzyszek2016-12-221-2/+2
| | | | | | | | | | | | | | | When the pipeliner is renaming phi values, it may need to iterate through the phi operands to check for other phis. However, the pipeliner should stop once it reaches a phi that is outside the pipelined loop. Also, when the generateExistingPhis code is unable to reuse an existing phi, the default code that computes the PhiOp2 is only to be used when the pipeliner is generating the kernel. Otherwise, the phi may be a value computed earlier in the same epilog. Patch by Brendon Cahoon. llvm-svn: 290355
* Fix an assertion in DwarfExpression when emitting fragments in vector registersAdrian Prantl2016-12-222-5/+20
| | | | | | | | | | | | | When DwarfExpression is emitting a fragment that is located in a register and that fragment is smaller than the register, and the register must be composed from sub-registers (are you still with me?) the last DW_OP_piece operation must not be larger than the size of the fragment itself, since the last piece of the fragment could be smaller than the last subregister that is being emitted. rdar://problem/29779065 llvm-svn: 290324
* Refactor the DIExpression fragment query interface (NFC)Adrian Prantl2016-12-226-16/+22
| | | | | | ... so it becomes available to DIExpressionCursor. llvm-svn: 290322
* DAG: Add helper for testing constant valuesMatt Arsenault2016-12-221-0/+10
| | | | | | | | There are helpers for testing for constant or constant build_vector, and for splat ConstantFP vectors, but not for a constantfp or non-splat ConstantFP vector. llvm-svn: 290317
* [X86] Vectorcall Calling Convention - Adding CodeGen Complete SupportOren Ben Simhon2016-12-212-2/+42
| | | | | | | | | | | | | The vectorcall calling convention specifies that arguments to functions are to be passed in registers, when possible. vectorcall uses more registers for arguments than fastcall or the default x64 calling convention use. The vectorcall calling convention is only supported in native code on x86 and x64 processors that include Streaming SIMD Extensions 2 (SSE2) and above. The current implementation does not handle Homogeneous Vector Aggregates (HVAs) correctly and this review attempts to fix it. This aubmit also includes additional lit tests to cover better HVAs corner cases. Differential Revision: https://reviews.llvm.org/D27392 llvm-svn: 290240
* machine combiner: fix pretty printerSebastian Pop2016-12-212-8/+10
| | | | | | | | | | | we used to print UNKNOWN instructions when the instruction to be printer was not yet inserted in any BB: in that case the pretty printer would not be able to compute a TII as the instruction does not belong to any BB or function yet. This patch explicitly passes the TII to the pretty-printer. Differential Revision: https://reviews.llvm.org/D27645 llvm-svn: 290228
* [Analysis] Centralize objectsize lowering logic.George Burgess IV2016-12-201-12/+2
| | | | | | | | | We're currently doing nearly the same thing for @llvm.objectsize in three different places: two of them are missing checks for overflow, and one of them could subtly break if InstCombine gets much smarter about removing alloc sites. Seems like a good idea to not do that. llvm-svn: 290214
* [IR] Remove the DIExpression field from DIGlobalVariable.Adrian Prantl2016-12-205-85/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements PR31013 by introducing a DIGlobalVariableExpression that holds a pair of DIGlobalVariable and DIExpression. Currently, DIGlobalVariables holds a DIExpression. This is not the best way to model this: (1) The DIGlobalVariable should describe the source level variable, not how to get to its location. (2) It makes it unsafe/hard to update the expressions when we call replaceExpression on the DIGLobalVariable. (3) It makes it impossible to represent a global variable that is in more than one location (e.g., a variable with multiple DW_OP_LLVM_fragment-s). We also moved away from attaching the DIExpression to DILocalVariable for the same reasons. This reapplies r289902 with additional testcase upgrades and a change to the Bitcode record for DIGlobalVariable, that makes upgrading the old format unambiguous also for variables without DIExpressions. <rdar://problem/29250149> https://llvm.org/bugs/show_bug.cgi?id=31013 Differential Revision: https://reviews.llvm.org/D26769 llvm-svn: 290153
* [CodeGen] Make MachineInstr::isIdenticalTo() symmetric.Bjorn Pettersson2016-12-191-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: MachineInstr::isIdenticalTo() is for some reason not symmetric when comparing bundles, which gives us the property: I1->isIdenticalTo(*I2) != I2->isIdenticalTo(*I1) when comparing bundles where one bundle is longer than the other. This patch makes sure that bundles of different length always are considered as not being identical. Thus, the result of the comparison will be the same regardless of which side that happens to be to the left. Reviewers: dexonsmith, jonpa, andrew.w.kaylor Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D27508 llvm-svn: 290095
* [XRay] Fix assertion failure on empty machine basic blocks (PR 31424)Dean Michael Berris2016-12-191-2/+9
| | | | | | | | | | | | | | | | | | | | The original version of the code in XRayInstrumentation.cpp assumed that functions may not have empty machine basic blocks (or that the first one couldn't be). This change addresses that by special-casing that specific situation. We provide two .mir test-cases to make sure we're handling this appropriately. Fixes llvm.org/PR31424. Reviewers: chandlerc Subscribers: varno, llvm-commits Differential Revision: https://reviews.llvm.org/D27913 llvm-svn: 290091
* Add custom type for PseudoSourceValueTom Stellard2016-12-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: PseudoSourceValue can be used to attach a target specific value for "well behaved" side-effects lowered from target specific intrinsics. This is useful whenever there is not an LLVM IR Value around when representing such "well behaved" side-effected operations in backends by attaching a MachineMemOperand with a custom PseudoSourceValue as this makes the scheduler not treating them as "GlobalMemoryObjects" which triggers a logic that makes the operation act like a barrier in the Schedule DAG. This patch adds another Kind to the PseudoSourceValue object which is "TargetCustom". It indicates a type of PseudoSourceValue that has a target specific meaning (aka. LLVM shouldn't assume any specific usage for such a PSV). It supports the possibility of having many different kinds of "TargetCustom" PseudoSourceValues. We had a discussion about if this was valuable or not (in particular because there was a believe that PSV were going away sooner or later) but seems like they are not going anywhere and I think they are useful backend side. It is not clear the interaction of this with MIRParser (do we need a target hook to parse these?) and I would like a comment from Alex about that :) Reviewers: arphaman, hfinkel, arsenm Subscribers: Eugene.Zelenko, llvm-commits Patch By: Marcello Maggioni Differential Revision: https://reviews.llvm.org/D13575 llvm-svn: 290037
* BranchRelaxation: Recompute live-ins when splitting a blockMatthias Braun2016-12-165-30/+44
| | | | | | | | Factors out and reuses live-in computation code from BranchFolding. Differential Revision: https://reviews.llvm.org/D27558 llvm-svn: 290013
* Allow "line 0" to be the first explicit debug location in a function.Paul Robinson2016-12-161-1/+1
| | | | | | Feedback on r289468 from Adrian Prantl. llvm-svn: 290012
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