summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
diff options
context:
space:
mode:
authorQuentin Colombet <qcolombet@apple.com>2016-12-22 21:56:26 +0000
committerQuentin Colombet <qcolombet@apple.com>2016-12-22 21:56:26 +0000
commit7e1f66d6f5d679632b279b64bb1a0f338104730c (patch)
tree3b0a14e14c1589cbc8eba82cb6360d523df42461 /llvm/lib/CodeGen
parentb4e71185b28ff60b47ecfe8ccae99e073562af25 (diff)
downloadbcm5719-llvm-7e1f66d6f5d679632b279b64bb1a0f338104730c.tar.gz
bcm5719-llvm-7e1f66d6f5d679632b279b64bb1a0f338104730c.zip
[RegisterBankInfo] Allow to set a register class when nothing else is set
This is going to be needed to be able to constraint register class on target specific instruction while the RegBankSelect pass did not run yet. llvm-svn: 290375
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp5
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index 34ec509b8ac..a6c93bc0f3d 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -224,12 +224,11 @@ const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister(
return MRI.constrainRegClass(Reg, &RC);
const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
- assert(RB && "Generic register does not have a register bank");
-
// Otherwise, all we can do is ensure the bank covers the class, and set it.
- if (!RB->covers(RC))
+ if (RB && !RB->covers(RC))
return nullptr;
+ // If nothing was set or the class is simply compatible, set it.
MRI.setRegClass(Reg, &RC);
return &RC;
}
OpenPOWER on IntegriCloud