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* [CMake] NFC. Updating CMake dependency specificationsChris Bieneman2016-11-175-10/+15
| | | | | | This patch updates a bunch of places where add_dependencies was being explicitly called to add dependencies on intrinsics_gen to instead use the DEPENDS named parameter. This cleanup is needed for a patch I'm working on to add a dependency debugging mode to the build system. llvm-svn: 287206
* [CodeGen] Pass references, not pointers, to MMI helpers. NFC.Ahmed Bougacha2016-11-164-13/+13
| | | | | | While there, rename them to follow the coding style. llvm-svn: 287169
* Revert "Get GlobalISel to build on Linux after r286407"Ahmed Bougacha2016-11-161-1/+1
| | | | | | | | | This reverts commit r286962. We want to avoid depending on SelectionDAG, and AddLandingPadInfo lives in CodeGen now. llvm-svn: 287168
* [CodeGen] Pull MMI helpers from FunctionLoweringInfo to MMI. NFC.Ahmed Bougacha2016-11-163-57/+51
| | | | | | | | | | | They're not SelectionDAG- or FunctionLoweringInfo-specific. They are, however, specific to building MMI from IR. We could make them members, but it's nice having MMI be a "simple" data structure and this logic kept separate. This also lets us reuse them from GlobalISel. llvm-svn: 287167
* [CodeGen] Cleanup MachineModuleInfo doxygen comments. NFC.Ahmed Bougacha2016-11-161-39/+7
| | | | | | Remove redundant names and only keep header comments. llvm-svn: 287166
* [ImplicitNullChecks] Do not not handle call MachineInstrsSanjoy Das2016-11-161-1/+4
| | | | | | | | | | | We don't track callee clobbered registers correctly, so avoid hoisting across calls. Note: for this bug to trigger we need a `readonly` call target, since we already have logic to not hoist across potentially storing instructions either. llvm-svn: 287159
* Make block placement deterministicRong Xu2016-11-161-3/+3
| | | | | | | | | | | | We fail to produce bit-to-bit matching stage2 and stage3 compiler in PGO bootstrap build. The reason is because LoopBlockSet is of SmallPtrSet type whose iterating order depends on the pointer value. This patch fixes this issue by changing to use SmallSetVector. Differential Revision: http://reviews.llvm.org/D26634 llvm-svn: 287148
* [RegAllocGreedy] Record missed hint for late recoloring.Quentin Colombet2016-11-161-0/+3
| | | | | | | | | | | | | | | In https://reviews.llvm.org/D25347, Geoff noticed that we still have useless copy that we can eliminate after register allocation. At the time the allocation is chosen for those copies, they are not useless but, because of changes in the surrounding code, later on they might become useless. The Greedy allocator already has a mechanism to deal with such cases with a late recoloring. However, we missed to record the some of the missed hints. This commit fixes that. llvm-svn: 287070
* Integer legalization: fix MUL expansionPawel Bylica2016-11-151-4/+4
| | | | | | | | | | | | | | | Summary: This fixes the runtime results produces by the fallback multiplication expansion introduced in r270720. For tests I created a fuzz tester that compares the results with Boost.Multiprecision. Reviewers: hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26628 llvm-svn: 286998
* Get GlobalISel to build on Linux after r286407Diana Picus2016-11-151-1/+1
| | | | | | | r286407 has introduced calls to llvm::AddLandingPadInfo, which lives in the SelectionDAG component. Add it to LLVMBuild to avoid linker failures on Linux. llvm-svn: 286962
* Introduce TLI predicative for base-relative Jump Tables.Joerg Sonnenberger2016-11-151-1/+1
| | | | | | | | | | | For 64bit ABIs it is common practice to use relative Jump Tables with potentially different relocation bases. As the logic for the jump table itself doesn't depend on the relocation base, make it easier for targets to use the generic logic. Start by dropping the now redundant MIPS logic. Differential Revision: https://reviews.llvm.org/D26578 llvm-svn: 286951
* DAGCombiner: fix combine of trunc and selectAsaf Badouh2016-11-151-1/+1
| | | | | | | | | | | | | bugzilla: https://llvm.org/bugs/show_bug.cgi?id=29002 pr29002 Differential Revision: https://reviews.llvm.org/D26449 llvm-svn: 286938
* MIRParser: Add support for parsing vreg reg alloc hintsTom Stellard2016-11-153-2/+30
| | | | | | | | | | Reviewers: qcolombet, MatzeB Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D26573 llvm-svn: 286911
* RegAllocGreedy: Properly initialize this pass, so that -run-pass will workTom Stellard2016-11-142-13/+19
| | | | | | | | | | Reviewers: qcolombet, MatzeB Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D26572 llvm-svn: 286895
* [tsan] Add support for C++ exceptions into TSan (call __tsan_func_exit ↵Kuba Brecka2016-11-141-115/+1
| | | | | | | | | | during unwinding), LLVM part This adds support for TSan C++ exception handling, where we need to add extra calls to __tsan_func_exit when a function is exitted via exception mechanisms. Otherwise the shadow stack gets corrupted (leaked). This patch moves and enhances the existing implementation of EscapeEnumerator that finds all possible function exit points, and adds extra EH cleanup blocks where needed. Differential Revision: https://reviews.llvm.org/D26177 llvm-svn: 286893
* Remove redundant condition (PR28800) NFCI.Simon Pilgrim2016-11-141-2/+1
| | | | | | | | | | 'A || (!A && B)' is equivalent to 'A || B': (LoopCycle > DefCycle) || (LoopCycle <= DefCycle && LoopStage <= DefStage) --> (LoopCycle > DefCycle) || (LoopStage <= DefStage) llvm-svn: 286811
* GlobalISel: Fix indentation. NFCDiana Picus2016-11-141-3/+3
| | | | llvm-svn: 286808
* Bitcode: Change module reader functions to return an llvm::Expected.Peter Collingbourne2016-11-131-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D26562 llvm-svn: 286752
* Revert "(origin/master, origin/HEAD) MachineScheduler/ScheduleDAG: Add ↵Matthias Braun2016-11-112-11/+0
| | | | | | | | | | support to skipping a node." Revert accidentally committed change. This reverts commit r286655. llvm-svn: 286656
* MachineScheduler/ScheduleDAG: Add support to skipping a node.Matthias Braun2016-11-112-0/+11
| | | | | | | | | | | The DAG mutators in the scheduler cannot really remove DAG nodes as additional anlysis information such as ScheduleDAGToplogicalSort are already computed at this point and rely on a fixed number of DAG nodes. Alleviate the missing removal with a new flag: Setting the new skip flag on a node ignores it during scheduling. llvm-svn: 286655
* ScheduleDAGInstrs: Move VRegUses to ScheduleDAGMILive; NFCIMatthias Braun2016-11-112-43/+43
| | | | | | | | | | | | | Push VRegUses/collectVRegUses() down the class hierarchy towards its only user ScheduleDAGMILive. NFCI: The initialization of the map happens at a later point but that should not matter. This is in preparation to allow DAG mutators to merge nodes, which relies on this map getting computed later. llvm-svn: 286654
* MachineScheduler: Dump EntrySU/ExitSU if possibleMatthias Braun2016-11-111-2/+12
| | | | llvm-svn: 286653
* ScheduleDAG: Identify EntrySU/ExitSU when dumping node idsMatthias Braun2016-11-111-3/+13
| | | | llvm-svn: 286652
* Simplify code and address review comments (NFC)Adrian Prantl2016-11-111-4/+3
| | | | llvm-svn: 286644
* Fix a reference-to-temporary introduced in r286607.Adrian Prantl2016-11-111-8/+10
| | | | llvm-svn: 286640
* Revert "Use private linkage for MergedGlobals variables" on Darwin.Adrian Prantl2016-11-111-3/+25
| | | | | | | | | | | | | | | | | | | This is a partial revert of r244615 (http://reviews.llvm.org/D11942), which caused a major regression in debug info quality. Turning the artificial __MergedGlobal symbols into private symbols (l__MergedGlobal) means that the linker will not include them in the symbol table of the final executable. Without a symbol table entry dsymutil is not be able to process the debug info for any of the merged globals and thus drops the debug info for all of them. This patch is enabling the old behavior for all MachO targets while leaving all other targets unaffected. rdar://problem/29160481 https://reviews.llvm.org/D26531 llvm-svn: 286607
* [SelectionDAG] Add support for vector demandedelts in BSWAP opcodesSimon Pilgrim2016-11-111-1/+2
| | | | llvm-svn: 286582
* [SelectionDAG] Add support for vector demandedelts in UREM/SREM opcodesSimon Pilgrim2016-11-111-6/+10
| | | | llvm-svn: 286578
* [SelectionDAG] Add support for vector demandedelts in UDIV opcodesSimon Pilgrim2016-11-111-2/+4
| | | | llvm-svn: 286576
* Split Bitcode/ReaderWriter.h into separate reader and writer headersTeresa Johnson2016-11-111-1/+2
| | | | | | | | | | | | | | | | | | | | | Summary: Split ReaderWriter.h which contains the APIs into both the BitReader and BitWriter libraries into BitcodeReader.h and BitcodeWriter.h. This is to address Chandler's concern about sharing the same API header between multiple libraries (BitReader and BitWriter). That concern is why we create a single bitcode library in our downstream build of clang, which led to r286297 being reverted as it added a dependency that created a cycle only when there is a single bitcode library (not two as in upstream). Reviewers: mehdi_amini Subscribers: dlj, mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D26502 llvm-svn: 286566
* ScheduleDAGInstrs: Add condjump deps to addSchedBarrierDeps()Matthias Braun2016-11-112-37/+24
| | | | | | | | | | | | | | | addSchedBarrierDeps() is supposed to add use operands to the ExitSU node. The current implementation adds uses for calls/barrier instruction and the MBB live-outs in all other cases. The use operands of conditional jump instructions were missed. Also added code to macrofusion to set the latencies between nodes to zero to avoid problems with the fusing nodes lingering around in the pending list now. Differential Revision: https://reviews.llvm.org/D25140 llvm-svn: 286544
* ScheduleDAGInstrs: Ignore dependencies of constant physregsMatthias Braun2016-11-101-0/+3
| | | | | | | | | There is no need to track dependencies for constant physregs, as they don't change their value no matter in what order you read/write to them. Differential Revision: https://reviews.llvm.org/D26221 llvm-svn: 286526
* [DAG Combiner] Fix the native computation of the Newton series for reciprocalsEvandro Menezes2016-11-101-28/+30
| | | | | | | | | | | | The generic infrastructure to compute the Newton series for reciprocal and reciprocal square root was conceived to allow a target to compute the series itself. However, the original code did not properly consider this condition if returned by a target. This patch addresses the issues to allow a target to compute the series on its own. Differential revision: https://reviews.llvm.org/D22975 llvm-svn: 286523
* [SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodesSimon Pilgrim2016-11-101-3/+6
| | | | llvm-svn: 286516
* ScheduleDAGInstrs: Slightly simplify code; NFCMatthias Braun2016-11-101-20/+12
| | | | llvm-svn: 286510
* [SelectionDAG] Add support for splatted vectors in SUB opcodeSimon Pilgrim2016-11-101-1/+1
| | | | llvm-svn: 286509
* RegisterCoalescer: Ignore interferences for constant physregsMatthias Braun2016-11-101-21/+25
| | | | | | | | | | | When copying to/from a constant register interferences can be ignored. Also update the documentation for isConstantPhysReg() to make it more obvious that this transformation is valid. Differential Revision: https://reviews.llvm.org/D26106 llvm-svn: 286503
* [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodesSimon Pilgrim2016-11-101-1/+2
| | | | llvm-svn: 286481
* Use common SDLoc. NFCI.Simon Pilgrim2016-11-101-3/+3
| | | | llvm-svn: 286473
* [SelectionDAG] Add support for vector demandedelts in MUL opcodesSimon Pilgrim2016-11-101-3/+5
| | | | llvm-svn: 286471
* [SelectionDAG] Add support for vector demandedelts in SRA opcodesSimon Pilgrim2016-11-101-1/+2
| | | | llvm-svn: 286461
* [DAGCombiner] Correctly extract the ConstOrConstSplat shift value for SHL nodesSimon Pilgrim2016-11-101-3/+2
| | | | | | | | We were failing to extract a constant splat shift value if the shifted value was being masked. The (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV) combine was unnecessarily preventing this. llvm-svn: 286454
* [SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodesSimon Pilgrim2016-11-101-2/+4
| | | | llvm-svn: 286448
* GlobalISel: fix typo. NFCTim Northover2016-11-091-2/+2
| | | | llvm-svn: 286408
* GlobalISel: translate invoke and landingpad instructionsTim Northover2016-11-091-1/+116
| | | | | | | Pretty bare-bones support for exception handling (no weird MSVC stuff, no SjLj etc), but it should get things going. llvm-svn: 286407
* [MachineScheduler] Comments fixing.Jonas Paulsson2016-11-091-1/+2
| | | | | | | | The name/comment of the third argument to the ScheduleDAGMI constructor is RemoveKillFlags and not IsPostRA. Only the comments are changed. Review: A Trick llvm-svn: 286350
* [CodeView] Hook up CodeViewRecordIO to type serialization path.Zachary Turner2016-11-082-97/+111
| | | | | | | | | | | | Previously support had been added for using CodeViewRecordIO to read (deserialize) CodeView type records. This patch adds support for writing those same records. With this patch, reading and writing of CodeView type records finally uses a single codepath. Differential Revision: https://reviews.llvm.org/D26253 llvm-svn: 286304
* Emit the DW_AT_type for a C++ static member definitionAdrian Prantl2016-11-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | if it is more specific than the one in its DW_AT_specification. If a static member is an array, the translation unit containing the member definition may have a more specific type (including its length) than TUs only seeing the class declaration. This patch adds a DW_AT_type to the member's DW_TAG_variable in addition to the DW_AT_specification in these cases. The member type in the DW_AT_specification still shows the more generic type (without the length) to avoid defeating type uniquing. The DWARF standard discourages “duplicating” a DW_AT_type in a member variable definition but doesn’t explicitly forbid it. Having the more specific type (with the array length) available is what allows the debugger to print the contents of a static array member variable. https://reviews.llvm.org/D26368 rdar://problem/28706946 llvm-svn: 286302
* GlobalISel: make sure debugging variables are appropriately elided in ↵David L. Jones2016-11-081-2/+4
| | | | | | | | | | | | | | | | release builds. Summary: There are two variables here that break. This change constrains both of them to debug builds (via DEBUG() or #ifndef NDEBUG). Reviewers: bkramer, t.p.northover Subscribers: mehdi_amini, vkalintiris Differential Revision: https://reviews.llvm.org/D26421 llvm-svn: 286300
* GlobalISel: allow CodeGen to fallback on VReg type/class issues.Tim Northover2016-11-082-25/+38
| | | | | | | | | After instruction selection we perform some checks on each VReg just before discarding the type information. These checks were assertions before, but that breaks the fallback path so this patch moves the logic into the main flow and reports a better error on failure. llvm-svn: 286289
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