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authorMatthias Braun <matze@braunis.de>2016-11-10 21:22:47 +0000
committerMatthias Braun <matze@braunis.de>2016-11-10 21:22:47 +0000
commit9d62c5571bd435e087be5247caed530247faf552 (patch)
tree90eeef45a774e78a4e36da7f72173c4190d581b0 /llvm/lib/CodeGen
parentd6fbe65040a91483035d7de8f7accd07449abfd4 (diff)
downloadbcm5719-llvm-9d62c5571bd435e087be5247caed530247faf552.tar.gz
bcm5719-llvm-9d62c5571bd435e087be5247caed530247faf552.zip
RegisterCoalescer: Ignore interferences for constant physregs
When copying to/from a constant register interferences can be ignored. Also update the documentation for isConstantPhysReg() to make it more obvious that this transformation is valid. Differential Revision: https://reviews.llvm.org/D26106 llvm-svn: 286503
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/RegisterCoalescer.cpp46
1 files changed, 25 insertions, 21 deletions
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 2c1a626af53..9705efccb6e 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1570,11 +1570,13 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
// Deny any overlapping intervals. This depends on all the reserved
// register live ranges to look like dead defs.
- for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI)
- if (RHS.overlaps(LIS->getRegUnit(*UI))) {
- DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
- return false;
- }
+ if (!MRI->isConstantPhysReg(DstReg)) {
+ for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI)
+ if (RHS.overlaps(LIS->getRegUnit(*UI))) {
+ DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
+ return false;
+ }
+ }
// Skip any value computations, we are not adding new values to the
// reserved register. Also skip merging the live ranges, the reserved
@@ -1596,24 +1598,26 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
const SlotIndex CopyRegIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
const SlotIndex DestRegIdx = LIS->getInstructionIndex(*DestMI).getRegSlot();
- // We checked above that there are no interfering defs of the physical
- // register. However, for this case, where we intent to move up the def of
- // the physical register, we also need to check for interfering uses.
- SlotIndexes *Indexes = LIS->getSlotIndexes();
- for (SlotIndex SI = Indexes->getNextNonNullIndex(DestRegIdx);
- SI != CopyRegIdx; SI = Indexes->getNextNonNullIndex(SI)) {
- MachineInstr *MI = LIS->getInstructionFromIndex(SI);
- if (MI->readsRegister(DstReg, TRI)) {
- DEBUG(dbgs() << "\t\tInterference (read): " << *MI);
- return false;
- }
-
- // We must also check for clobbers caused by regmasks.
- for (const auto &MO : MI->operands()) {
- if (MO.isRegMask() && MO.clobbersPhysReg(DstReg)) {
- DEBUG(dbgs() << "\t\tInterference (regmask clobber): " << *MI);
+ if (!MRI->isConstantPhysReg(DstReg)) {
+ // We checked above that there are no interfering defs of the physical
+ // register. However, for this case, where we intent to move up the def of
+ // the physical register, we also need to check for interfering uses.
+ SlotIndexes *Indexes = LIS->getSlotIndexes();
+ for (SlotIndex SI = Indexes->getNextNonNullIndex(DestRegIdx);
+ SI != CopyRegIdx; SI = Indexes->getNextNonNullIndex(SI)) {
+ MachineInstr *MI = LIS->getInstructionFromIndex(SI);
+ if (MI->readsRegister(DstReg, TRI)) {
+ DEBUG(dbgs() << "\t\tInterference (read): " << *MI);
return false;
}
+
+ // We must also check for clobbers caused by regmasks.
+ for (const auto &MO : MI->operands()) {
+ if (MO.isRegMask() && MO.clobbersPhysReg(DstReg)) {
+ DEBUG(dbgs() << "\t\tInterference (regmask clobber): " << *MI);
+ return false;
+ }
+ }
}
}
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