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* Correct dwarf unwind information in function epilogue for X86Petar Jovanovic2017-11-017-14/+420
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: - CFI instructions do not affect code generation - Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Changed CFI instructions so that they: - are duplicable - are not counted as instructions when tail duplicating or tail merging - can be compared as equal Added CFIInstrInserter pass: - analyzes each basic block to determine cfa offset and register valid at its entry and exit - verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors - inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D35844 llvm-svn: 317100
* [SelectionDAG] computeKnownBits - use ashrInPlace on known bits of ISD::SRA ↵Simon Pilgrim2017-11-011-11/+3
| | | | | | input. NFCI. llvm-svn: 317087
* [DAGCombiner] Fix typos in comments. NFCCraig Topper2017-11-011-2/+2
| | | | llvm-svn: 317072
* [codeview] Merge file checksum entries for DIFiles with the same absolute pathReid Kleckner2017-10-312-4/+5
| | | | | | | | Change the map key from DIFile* to the absolute path string. Computing the absolute path isn't expensive because we already have a map that caches the full path keyed on DIFile*. llvm-svn: 317041
* [CGP] Fix the detection of trivial case for addressing modeSerguei Katkov2017-10-311-10/+9
| | | | | | | The address can be presented as a bitcast of baseReg. In this case it is still trivial but OriginalValue != baseReg. llvm-svn: 316980
* [CGP] Fix crash on i96 bit multiplyPhilip Reames2017-10-301-1/+1
| | | | | | | | Issue found by llvm-isel-fuzzer on OSS fuzz, https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3725 If anyone actually cares about > 64 bit arithmetic, there's a lot more to do in this area. There's a bunch of obviously wrong code in the same function. I don't have the time to fix all of them and am just using this to understand what the workflow for fixing fuzzer cases might look like. llvm-svn: 316967
* Fix unused variable warnings. NFCI.Simon Pilgrim2017-10-301-3/+0
| | | | llvm-svn: 316964
* [SelectionDAG] Tidyup computeKnownBits extension/truncation cases. NFCI.Simon Pilgrim2017-10-301-17/+4
| | | | | | We don't need to extend/truncate the Known structure before calling computeKnownBits - it will reset at the start of the function. llvm-svn: 316962
* Create instruction classes for identifying any atomicity of memory ↵Daniel Neilson2017-10-301-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | intrinsic. (NFC) Summary: For reference, see: http://lists.llvm.org/pipermail/llvm-dev/2017-August/116589.html This patch fleshes out the instruction class hierarchy with respect to atomic and non-atomic memory intrinsics. With this change, the relevant part of the class hierarchy becomes: IntrinsicInst -> MemIntrinsicBase (methods-only class) -> MemIntrinsic (non-atomic intrinsics) -> MemSetInst -> MemTransferInst -> MemCpyInst -> MemMoveInst -> AtomicMemIntrinsic (atomic intrinsics) -> AtomicMemSetInst -> AtomicMemTransferInst -> AtomicMemCpyInst -> AtomicMemMoveInst -> AnyMemIntrinsic (both atomicities) -> AnyMemSetInst -> AnyMemTransferInst -> AnyMemCpyInst -> AnyMemMoveInst This involves some class renaming: ElementUnorderedAtomicMemCpyInst -> AtomicMemCpyInst ElementUnorderedAtomicMemMoveInst -> AtomicMemMoveInst ElementUnorderedAtomicMemSetInst -> AtomicMemSetInst A script for doing this renaming in downstream trees is included below. An example of where the Any* classes should be used in LLVM is when reasoning about the effects of an instruction (ex: aliasing). --- Script for renaming AtomicMem* classes: PREFIXES="[<,([:space:]]" CLASSES="MemIntrinsic|MemTransferInst|MemSetInst|MemMoveInst|MemCpyInst" SUFFIXES="[;)>,[:space:]]" REGEX="(${PREFIXES})ElementUnorderedAtomic(${CLASSES})(${SUFFIXES})" REGEX2="visitElementUnorderedAtomic(${CLASSES})" FILES=$( grep -E "(${REGEX}|${REGEX2})" -r . | tr ':' ' ' | awk '{print $1}' | sort | uniq ) SED_SCRIPT="s~${REGEX}~\1Atomic\2\3~g" SED_SCRIPT2="s~${REGEX2}~visitAtomic\1~g" for f in $FILES; do echo "Processing: $f" sed -i ".bak" -E "${SED_SCRIPT};${SED_SCRIPT2};${EA_SED_SCRIPT};${EA_SED_SCRIPT2}" $f done Reviewers: sanjoy, deadalnix, apilipenko, anna, skatkov, mkazantsev Reviewed By: sanjoy Subscribers: hfinkel, jholewinski, arsenm, sdardis, nhaehnle, JDevlieghere, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D38419 llvm-svn: 316950
* [SelectionDAG] Add VSELECT demanded elts support to computeKnownBits Simon Pilgrim2017-10-301-4/+4
| | | | llvm-svn: 316947
* [SelectionDAG] Add VSELECT support to computeKnownBits Simon Pilgrim2017-10-301-0/+1
| | | | llvm-svn: 316944
* [SelectionDAG] Add SELECT demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-301-4/+5
| | | | llvm-svn: 316933
* [MC] Split out register def/use idx calls to make debugging simpler. NFCI.Simon Pilgrim2017-10-301-3/+4
| | | | llvm-svn: 316927
* [CodeGen][ExpandMemcmp] Allow memcmp to expand to vector loads (2).Clement Courbet2017-10-301-25/+26
| | | | | | | | | | | | - Targets that want to support memcmp expansions now return the list of supported load sizes. - Expansion codegen does not assume that all power-of-two load sizes smaller than the max load size are valid. For examples, this is not the case for x86(32bit)+sse2. Fixes PR34887. llvm-svn: 316905
* [GlobalISel|ARM] : Allow legalizing G_FSUBJaved Absar2017-10-301-0/+4
| | | | | | | | Adding support for VSUB. Reviewed by: @rovka Differential Revision: https://reviews.llvm.org/D39261 llvm-svn: 316902
* [SelectionDAG] Add SEXT/AND/XOR/Or demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-291-7/+11
| | | | llvm-svn: 316875
* [SelectionDAG] Add SRA/SHL demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-291-3/+29
| | | | | | Introduce a isConstOrDemandedConstSplat helper function that can recognise a constant splat build vector for at least the demanded elts we care about. llvm-svn: 316866
* [SelectionDAG] Add support for INSERT_SUBVECTOR to computeKnownBitsSimon Pilgrim2017-10-281-0/+34
| | | | llvm-svn: 316847
* [SelectionDAG] Support 'bit preserving' floating points bitcasts on ↵Simon Pilgrim2017-10-281-7/+15
| | | | | | | | | | | | computeKnownBits/ComputeNumSignBits For cases where we know the floating point representations match the bitcasted integer equivalent, allow bitcasting to these types. This is especially useful for the X86 floating point compare results which return all/zero bits but as a floating point type. Differential Revision: https://reviews.llvm.org/D39289 llvm-svn: 316831
* Add a few missing headers for modularization/IWYU/etcDavid Blaikie2017-10-271-1/+1
| | | | | | | Several cases where class definitions are required for DenseMap pointer traits handling. llvm-svn: 316803
* [DAGCombine] Don't combine sext with extload if sextload is not supported ↵Guozhi Wei2017-10-271-1/+5
| | | | | | | | | | | | | | | and extload has multi users In function DAGCombiner::visitSIGN_EXTEND_INREG, sext can be combined with extload even if sextload is not supported by target, then if sext is the only user of extload, there is no big difference, no harm no benefit. if extload has more than one user, the combined sextload may block extload from combining with other zext, causes extra zext instructions generated. As demonstrated by the attached test case. This patch add the constraint that when sextload is not supported by target, sext can only be combined with extload if it is the only user of extload. Differential Revision: https://reviews.llvm.org/D39108 llvm-svn: 316802
* [CodeGen] Fix -Wunused-private-field warning on lld-x86_64-darwin13.Clement Courbet2017-10-271-2/+0
| | | | llvm-svn: 316765
* [CodeGen][ExpandMemCmp][NFC] Simplify load sequence generation.Clement Courbet2017-10-271-40/+33
| | | | llvm-svn: 316763
* DAG: Fold fma (fneg x), K, y -> fma x, -K, yMatt Arsenault2017-10-271-0/+8
| | | | llvm-svn: 316753
* Add subclass data to the FoldingSetNode for MemIntrinsicSDNodes.Sean Fertile2017-10-271-0/+2
| | | | | | | | | | | Not having the subclass data on an MemIntrinsicSDNodes means it was possible to try to fold 2 nodes with the same operands but differing MMO flags. This would trip an assertion when trying to refine the alignment between the 2 MachineMemOperands. Differential Revision: https://reviews.llvm.org/D38898 llvm-svn: 316737
* Revert "[CGP] Merge empty case blocks if no extra moves are added."Balaram Makam2017-10-271-36/+11
| | | | | | This reverts commit r316711. The domtree isn't getting updated correctly. llvm-svn: 316721
* [CGP] Merge empty case blocks if no extra moves are added.Balaram Makam2017-10-261-11/+36
| | | | | | | | | | | | | | | | Summary: Currently we skip merging when extra moves may be added in the header of switch instead of the case block, if the case block is used as an incoming block of a PHI. If all the incoming values of the PHIs are non-constants and the destination block is dominated by the switch block then extra moves are likely not added by ISel, so there is no need to skip merging in this case. Reviewers: efriedma, junbuml, davidxl, hfinkel, qcolombet Reviewed By: efriedma Subscribers: dberlin, kuhar, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D37343 llvm-svn: 316711
* [MachineModuleInfoImpls] Replace qsort with array_pod_sortMandeep Singh Grang2017-10-261-10/+4
| | | | | | | | | | | | | | | | Summary: This seems to be the only place in llvm we directly call qsort. We can replace this with a call to array_pod_sort. Also minor cleanup of the sorting function. Reviewers: bkramer, Eugene.Zelenko, rafael Reviewed By: bkramer Subscribers: efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D39214 llvm-svn: 316671
* Tidy up CountingFunctionInserter a little. NFC.Hans Wennborg2017-10-261-8/+4
| | | | | | | Use StringRef for CountingFunctionName, remove erroneous comment copied from InstructionNamer, and drop some trailing whitespace. llvm-svn: 316644
* Make the combiner check if shifts are legal before creating themAditya Nandakumar2017-10-251-2/+3
| | | | | | | | | | | | Summary: Make sure shifts are legal/specified by the legalizerinfo before creating it Reviewers: qcolombet, dsanders, rovka, t.p.northover Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39264 llvm-svn: 316602
* Re-land "[CodeGen][ExpandMemcmp][NFC] Allow memcmp to expand to vector loads ↵Clement Courbet2017-10-251-195/+227
| | | | | | | | | | | | | (1)" Compute the actual decomposition only after deciding whether to expand of not. Else, it's easy to make the compiler OOM with: `memcpy(dst, src, 0xffffffffffffffff);`, which typically happens if someone mistakenly passes a negative value. Add a test. This reverts commit f8fc02fbd4ab33383c010d33675acf9763d0bd44. llvm-svn: 316567
* [MachineScheduler] Minor refactoring.Jonas Paulsson2017-10-251-13/+18
| | | | | | | | | | | | | | | | Duplicated code found in three places put into a new static function: /// Given a Count of resource usage and a Latency value, return true if a /// SchedBoundary becomes resource limited. static bool checkResourceLimit(unsigned LFactor, unsigned Count, unsigned Latency) { return (int)(Count - (Latency * LFactor)) > (int)LFactor; } Review: Florian Hahn, Matthias Braun https://reviews.llvm.org/D39235 llvm-svn: 316560
* DAG: Fix creating select with wrong condition typeMatt Arsenault2017-10-251-1/+10
| | | | | | | | | | | | | | | | | | | This code added in r297930 assumed that it could create a select with a condition type that is just an integer bitcast of the selected type. For AMDGPU any vselect is going to be scalarized (although the vector types are legal), and all select conditions must be i1 (the same as getSetCCResultType). This logic doesn't really make sense to me, but there's never really been a consistent policy in what the select condition mask type is supposed to be. Try to extend the logic for skipping the transform for condition types that aren't setccs. It doesn't seem quite right to me though, but checking conditions that seem more sensible (like whether the vselect is going to be expanded) doesn't work since this seems to depend on that also. llvm-svn: 316554
* Implement salavageDebugInfo functionality for SelectionDAG.Adrian Prantl2017-10-242-0/+35
| | | | | | | | | | | | | | Similar to how llvm::salvagDebugInfo hooks into InstCombine, this adds a hook that can be invoked before an SDNode that is associated with an SDDbgValue is erased to capture the effect of the deleted node in a DIExpression. The motivating example is an SDDebugValue attached to an ADD operation that gets folded into a LOAD+OFFSET operation. rdar://problem/32121503 llvm-svn: 316525
* Revert "[CodeGen][ExpandMemcmp][NFC] Allow memcmp to expand to vector loads (1)"Martin Bohme2017-10-241-201/+196
| | | | | | | | This reverts commit r316417, which causes internal compiles to OOM. I don't unfortunately have a self-contained test case but will follow up with courbet. llvm-svn: 316497
* Use range-based for loop. NFCAdrian Prantl2017-10-241-5/+2
| | | | llvm-svn: 316496
* Use range-based-for. NFCAdrian Prantl2017-10-241-6/+5
| | | | llvm-svn: 316485
* MIR: Print the register class or bank in vreg defsJustin Bogner2017-10-241-12/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
* Doxygenify comments.Adrian Prantl2017-10-241-26/+25
| | | | llvm-svn: 316466
* [SelectionDAG] Add VSELECT support to ComputeNumSignBitsSimon Pilgrim2017-10-241-0/+1
| | | | llvm-svn: 316457
* [CodeGen][ExpandMemcmp][NFC] Allow memcmp to expand to vector loads (1)Clement Courbet2017-10-241-196/+201
| | | | | | | | | | | | | | | | | | | | | | Refactor ExpandMemcmp: - Stop duplicating the logic for computation of the sequence of loads to generate (thsi was done in three different places), this is now done only once in MemCmpExpansion::MemCmpExpansion(). - Add a FIXME to expose a bug with the computation of the number of loads when not all sizes are loadable. For example, on X86-32 + SSE, possible loads are {16,4,2,1} bytes. The current code considers that all loads starting at MaxLoadSize are possible. This is not an issue right now as vector loads are not enabled, so I'm not fixing the issue here to keep the change as small as possible. I'm going to address this in a subsequent revision, where I enable vector loads. See https://bugs.llvm.org/show_bug.cgi?id=34887 Differential Revision: https://reviews.llvm.org/D38498 llvm-svn: 316417
* [MC] Adding code padding for performance stability - infrastructure. NFC.Omer Paparo Bivas2017-10-241-4/+29
| | | | | | | | | | | | | | | | | Infrastructure designed for padding code with nop instructions in key places such that preformance improvement will be achieved. The infrastructure is implemented such that the padding is done in the Assembler after the layout is done and all IPs and alignments are known. This patch by itself in a NFC. Future patches will make use of this infrastructure to implement required policies for code padding. Reviewers: aaboud zvi craig.topper gadi.haber Differential revision: https://reviews.llvm.org/D34393 Change-Id: I92110d0c0a757080a8405636914a93ef6f8ad00e llvm-svn: 316413
* [MachineOutliner] Add optimisation remarks for successful outliningJessica Paquette2017-10-231-36/+75
| | | | | | | | | | | | | | | | | | | This commit adds optimisation remarks for outlining which fire when a function is successfully outlined. To do this, OutlinedFunctions must now contain references to their Candidates. Since the Candidates must still be sorted and worked on separately, this is done by working on everything in terms of shared_ptrs to Candidates. This is good; it means that we can easily move everything to outlining in terms of the OutlinedFunctions rather than the individual Candidates. This is far more intuitive than what's currently there! (Remarks are output when a function is created for some group of Candidates. In a later commit, all of the outlining logic should be rewritten so that we loop over OutlinedFunctions rather than over Candidates.) llvm-svn: 316396
* Fix buildbot breakageGeorge Burgess IV2017-10-231-0/+1
| | | | | | SP is only used in an assert. Caused by r316374. llvm-svn: 316377
* Don't crash when we see unallocatable registers in clobbersGeorge Burgess IV2017-10-233-15/+34
| | | | | | | | | | | | | | This fixes a bug where we'd crash given code like the test-case from https://bugs.llvm.org/show_bug.cgi?id=30792 . Instead, we let the offending clobber silently slide through. This doesn't fully fix said bug, since the assembler will still complain the moment it sees a crypto/fp/vector op, and we still don't diagnose calls that require vector regs. Differential Revision: https://reviews.llvm.org/D39030 llvm-svn: 316374
* [MachineOutliner] NFC: Rename getters/setters to fit coding styleJessica Paquette2017-10-231-13/+13
| | | | | | | Rename endIdx, startIdx, and length to getEndIdx, getStartIdx, and getLength in Candidate. llvm-svn: 316341
* [DAGCombine] Permit combining of shuffles of equivalent splat BUILD_VECTORsSimon Pilgrim2017-10-231-5/+15
| | | | | | | | | | combineShuffleOfScalars is very conservative about shuffled BUILD_VECTORs that can be combined together. This patch adds one additional case - if both BUILD_VECTORs represent splats of the same scalar value but with different UNDEF elements, then we should create a single splat BUILD_VECTOR, sharing only the UNDEF elements defined by the shuffle mask. Differential Revision: https://reviews.llvm.org/D38696 llvm-svn: 316331
* Add logic to greedy reg alloc to avoid bad eviction chainsMarina Yatsina2017-10-224-20/+413
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes bugzilla 26810 https://bugs.llvm.org/show_bug.cgi?id=26810 This is intended to prevent sequences like: movl %ebp, 8(%esp) # 4-byte Spill movl %ecx, %ebp movl %ebx, %ecx movl %edi, %ebx movl %edx, %edi cltd idivl %esi movl %edi, %edx movl %ebx, %edi movl %ecx, %ebx movl %ebp, %ecx movl 16(%esp), %ebp # 4 - byte Reload Such sequences are created in 2 scenarios: Scenario #1: vreg0 is evicted from physreg0 by vreg1 Evictee vreg0 is intended for region splitting with split candidate physreg0 (the reg vreg0 was evicted from) Region splitting creates a local interval because of interference with the evictor vreg1 (normally region spliiting creates 2 interval, the "by reg" and "by stack" intervals. Local interval created when interference occurs.) one of the split intervals ends up evicting vreg2 from physreg1 Evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills Scenario #2 vreg0 is evicted from physreg0 by vreg1 vreg2 is evicted from physreg2 by vreg3 etc Evictee vreg0 is intended for region splitting with split candidate physreg1 Region splitting creates a local interval because of interference with the evictor vreg1 one of the split intervals ends up evicting back original evictor vreg1 from physreg0 (the reg vreg0 was evicted from) Another evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills As compile time was a concern, I've added a flag to control weather we do cost calculations for local intervals we expect to be created (it's on by default for X86 target, off for the rest). Differential Revision: https://reviews.llvm.org/D35816 Change-Id: Id9411ff7bbb845463d289ba2ae97737a1ee7cc39 llvm-svn: 316295
* [SelectionDAG] Use dyn_cast without cast.Florian Hahn2017-10-211-2/+2
| | | | llvm-svn: 316258
* [SelectionDAG] Use isa to silence unused variable warning (NFC).Florian Hahn2017-10-211-1/+1
| | | | llvm-svn: 316257
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