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authorSimon Pilgrim <llvm-dev@redking.me.uk>2017-10-30 22:23:57 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2017-10-30 22:23:57 +0000
commit80b371361cd6ad7bd47504e5521fdea53047ddea (patch)
tree6ddae2d79c4bd2cc819a74a719dd9c6052722f4e /llvm/lib/CodeGen
parent1128dc5e30e1d067f6408b5d80229e146aabb2ec (diff)
downloadbcm5719-llvm-80b371361cd6ad7bd47504e5521fdea53047ddea.tar.gz
bcm5719-llvm-80b371361cd6ad7bd47504e5521fdea53047ddea.zip
[SelectionDAG] Tidyup computeKnownBits extension/truncation cases. NFCI.
We don't need to extend/truncate the Known structure before calling computeKnownBits - it will reset at the start of the function. llvm-svn: 316962
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp21
1 files changed, 4 insertions, 17 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 16d157a3152..0e0b83fd875 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2567,32 +2567,23 @@ void SelectionDAG::computeKnownBits(SDValue Op, KnownBits &Known,
}
case ISD::ZERO_EXTEND_VECTOR_INREG: {
EVT InVT = Op.getOperand(0).getValueType();
- unsigned InBits = InVT.getScalarSizeInBits();
- Known = Known.trunc(InBits);
- computeKnownBits(Op.getOperand(0), Known,
- DemandedElts.zext(InVT.getVectorNumElements()),
- Depth + 1);
+ APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements());
+ computeKnownBits(Op.getOperand(0), Known, InDemandedElts, Depth + 1);
Known = Known.zext(BitWidth);
- Known.Zero.setBitsFrom(InBits);
+ Known.Zero.setBitsFrom(InVT.getScalarSizeInBits());
break;
}
case ISD::ZERO_EXTEND: {
EVT InVT = Op.getOperand(0).getValueType();
- unsigned InBits = InVT.getScalarSizeInBits();
- Known = Known.trunc(InBits);
computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
Known = Known.zext(BitWidth);
- Known.Zero.setBitsFrom(InBits);
+ Known.Zero.setBitsFrom(InVT.getScalarSizeInBits());
break;
}
// TODO ISD::SIGN_EXTEND_VECTOR_INREG
case ISD::SIGN_EXTEND: {
EVT InVT = Op.getOperand(0).getValueType();
- unsigned InBits = InVT.getScalarSizeInBits();
-
- Known = Known.trunc(InBits);
computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
-
// If the sign bit is known to be zero or one, then sext will extend
// it to the top bits, else it will just zext.
Known = Known.sext(BitWidth);
@@ -2600,16 +2591,12 @@ void SelectionDAG::computeKnownBits(SDValue Op, KnownBits &Known,
}
case ISD::ANY_EXTEND: {
EVT InVT = Op.getOperand(0).getValueType();
- unsigned InBits = InVT.getScalarSizeInBits();
- Known = Known.trunc(InBits);
computeKnownBits(Op.getOperand(0), Known, Depth+1);
Known = Known.zext(BitWidth);
break;
}
case ISD::TRUNCATE: {
EVT InVT = Op.getOperand(0).getValueType();
- unsigned InBits = InVT.getScalarSizeInBits();
- Known = Known.zext(InBits);
computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
Known = Known.trunc(BitWidth);
break;
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