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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-25 07:14:07 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-25 07:14:07 +0000 |
commit | 8a752b77a2868066237f9ec4c5c9b292f9983afa (patch) | |
tree | 46a4638b195b8f8d3e75ea06ba54e12d44a45ac5 /llvm/lib/CodeGen | |
parent | 28f52e51f1c6253abc6a2cf0203f834805ed3a2d (diff) | |
download | bcm5719-llvm-8a752b77a2868066237f9ec4c5c9b292f9983afa.tar.gz bcm5719-llvm-8a752b77a2868066237f9ec4c5c9b292f9983afa.zip |
DAG: Fix creating select with wrong condition type
This code added in r297930 assumed that it could create
a select with a condition type that is just an integer
bitcast of the selected type. For AMDGPU any vselect is
going to be scalarized (although the vector types are legal),
and all select conditions must be i1 (the same as getSetCCResultType).
This logic doesn't really make sense to me, but there's
never really been a consistent policy in what the select
condition mask type is supposed to be. Try to extend
the logic for skipping the transform for condition types
that aren't setccs. It doesn't seem quite right to me though,
but checking conditions that seem more sensible (like whether the
vselect is going to be expanded) doesn't work since this
seems to depend on that also.
llvm-svn: 316554
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 778573390eb..5d6c4998ecd 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -3101,7 +3101,8 @@ SDValue DAGTypeLegalizer::WidenVSELECTAndMask(SDNode *N) { // If this is a splitted VSELECT that was previously already handled, do // nothing. - if (Cond->getValueType(0).getScalarSizeInBits() != 1) + EVT CondVT = Cond->getValueType(0); + if (CondVT.getScalarSizeInBits() != 1) return SDValue(); EVT VSelVT = N->getValueType(0); @@ -3125,6 +3126,14 @@ SDValue DAGTypeLegalizer::WidenVSELECTAndMask(SDNode *N) { EVT SetCCResVT = getSetCCResultType(SetCCOpVT); if (SetCCResVT.getScalarSizeInBits() == 1) return SDValue(); + } else if (CondVT.getScalarType() == MVT::i1) { + // If there is support for an i1 vector mask (or only scalar i1 conditions), + // don't touch. + while (TLI.getTypeAction(Ctx, CondVT) != TargetLowering::TypeLegal) + CondVT = TLI.getTypeToTransformTo(Ctx, CondVT); + + if (CondVT.getScalarType() == MVT::i1) + return SDValue(); } // Get the VT and operands for VSELECT, and widen if needed. |