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* [DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded ↵Sanjay Patel2016-10-311-7/+18
| | | | | | | | | | | | | | | | bits (PR30841) This bug was exposed by using nsw/nuw for more aggressive folds in: https://reviews.llvm.org/rL284844 The changes mimic the IR demanded bits logic in InstCombiner::SimplifyDemandedUseBits(), but we can't just flip flag bits in the DAG; we have to create a new node that has the bits cleared. This should fix: https://llvm.org/bugs/show_bug.cgi?id=30841 llvm-svn: 285656
* DebugInfo: make DW_TAG_atomic_type validVictor Leschuk2016-10-313-3/+8
| | | | | | | | | | | | | | DW_TAG_atomic_type was already included in Dwarf.defs and emitted correctly, however Verifier didn't recognize it as valid. Thus we introduce the following changes: * Make DW_TAG_atomic_type valid tag for IR and DWARF (enabled only with -gdwarf-5) * Add it to related docs * Add DebugInfo tests Differential Revision: https://reviews.llvm.org/D26144 llvm-svn: 285624
* GlobalISel: translate stack protector intrinsicsTim Northover2016-10-312-13/+63
| | | | llvm-svn: 285614
* [DAG] x | x --> xSanjay Patel2016-10-301-0/+4
| | | | llvm-svn: 285522
* [DAG] x & x --> xSanjay Patel2016-10-301-0/+4
| | | | llvm-svn: 285521
* [DAGCombiner] (REAPPLIED) Add vector demanded elements support to ↵Simon Pilgrim2016-10-291-13/+111
| | | | | | | | | | | | | | | | | | | | computeKnownBits Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. This looked like this had caused compile time regressions on some buildbots (and was reverted in rL285381), but appears to have just been a harmless bystander! Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285494
* [DAGCombiner] Fix a crash visiting `AND` nodes.Davide Italiano2016-10-281-1/+6
| | | | | | | | | | Instead of asserting that the shift count is != 0 we just bail out as it's not profitable trying to optimize a node which will be removed anyway. Differential Revision: https://reviews.llvm.org/D26098 llvm-svn: 285480
* SDAG: Make sure we use an allocatable reg class when we create this vregJustin Bogner2016-10-281-0/+2
| | | | | | | As per the discussion on r280783, if constrainRegClass fails we need to call getAllocatableClass like we did before that commit. llvm-svn: 285467
* Handle non-~0 lane masks on live-in registers in LivePhysRegsKrzysztof Parzyszek2016-10-281-2/+3
| | | | | | | | | | | | | | | | | When LivePhysRegs adds live-in registers, it recognizes ~0 as a special lane mask indicating the entire register. If the lane mask is not ~0, it will only add the subregisters that overlap the specified lane mask. The problem is that if a live-in register does not have subregisters, and the lane mask is not ~0, it will not be added to the live set. (The given lane mask may simply be the lane mask of its register class.) If a register does not have subregisters, add it to the live set if the lane mask is non-zero. Differential Revision: https://reviews.llvm.org/D26094 llvm-svn: 285440
* MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFCMatthias Braun2016-10-286-7/+6
| | | | llvm-svn: 285423
* TargetPassConfig: Move addPass of IPRA RegUsageInfoProp down.Matthias Braun2016-10-281-3/+3
| | | | | | | | | TargetPassConfig::addMachinePasses() does some housekeeping first: Handling the -print-machineinstrs flag and doing an initial printing "After Instruction Selection". There is no reason for RegUsageInfoProp to run before those two steps. llvm-svn: 285422
* Import/update constants from the DWARF 5 public review draft document.Adrian Prantl2016-10-281-2/+2
| | | | | | https://reviews.llvm.org/D26051 llvm-svn: 285421
* [SelectionDAG] computeKnownBits - early-out if any BUILD_VECTOR element has ↵Simon Pilgrim2016-10-281-0/+4
| | | | | | | | no known bits No need to check the remaining elements - no common known bits are available. llvm-svn: 285399
* [SelectionDAG] Tidyup UDIV computeKnownBits implementationSimon Pilgrim2016-10-281-2/+0
| | | | | | No need to clear KnownOne2/KnownZero2 bits as the next call to computeKnownBits will overwrite them anyway llvm-svn: 285398
* [SelectionDAG] Increment computeKnownBits recursion depth for ↵Simon Pilgrim2016-10-281-2/+2
| | | | | | SMIN/SMAX/UMIN/UMAX like all other ops llvm-svn: 285397
* Revert "[DAGCombiner] Add vector demanded elements support to computeKnownBits"Juergen Ributzka2016-10-281-111/+13
| | | | | | | This seems to have increased LTO compile time bejond 2x of previous builds. See http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto/10676/ llvm-svn: 285381
* CodeGen: Handle missed case of block removal during BlockPlacement.Kyle Butt2016-10-271-4/+10
| | | | | | | | | There is a use after free bug in the existing code. Loop layout selects a preferred exit block, and then lays out the loop. If this block is removed during layout, it needs to be invalidated to prevent a use after free. llvm-svn: 285348
* Fix memory issue in AttrBuilder::removeAttribute uses.Bjorn Pettersson2016-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: Found when running Valgrind. This removes two unnecessary assignments when using AttrBuilder::removeAttribute. AttrBuilder::removeAttribute returns a reference to the object. As the LHSes were the same as the callees, the assignments resulted in memcpy calls where dst = src. Commited on behalf-of: dstenb (David Stenberg) Reviewers: mkuper, rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25460 llvm-svn: 285298
* [DAGCombiner] Add vector demanded elements support to computeKnownBitsSimon Pilgrim2016-10-271-13/+111
| | | | | | | | | | | | | | | | Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285296
* DebugInfo: fix incorrect alignment type (NFC)Victor Leschuk2016-10-261-3/+3
| | | | | | | | | Change type of some missed DebugInfo-related alignment variables, that are still uint64_t, to uint32_t. Original change introduced in r284482. llvm-svn: 285242
* Do not assume that FP vector operands are never legalized by expandingNemanja Ivanovic2016-10-261-1/+2
| | | | | | | | | | | This patch ensures that if a floating point vector operand is legalized by expanding, it is legalized through the stack rather than by calling DAGTypeLegalizer::IntegerToVector which will cause a failure since the operand is a non-integer type. This fixes PR 30715. llvm-svn: 285231
* Reapply: "Remove debug location from common tail when tail-merging"Robert Lougher2016-10-261-2/+5
| | | | | | | | | | | | | | | | This reapplies revision 285093. Original commit message: The branch folding pass tail merges blocks into a common-tail. However, the tail retains the debug information from one of the original inputs to the merge (chosen randomly). This is a problem for sampled-based PGO, as hits on the common-tail will be attributed to whichever block was chosen, irrespective of which path was actually taken to the common-tail. This patch fixes the issue by nulling the debug location for the common-tail. Differential Revision: https://reviews.llvm.org/D25742 llvm-svn: 285212
* Fix nondeterministic output in local stack slot alloc passMatt Arsenault2016-10-261-6/+16
| | | | | | | | | | This finds all of the references to a frame index in a function, and sorts by the offset. If multiple instructions use the same offset, nothing was breaking the tie for sorting. This avoids the test failures the reverted r282999 introduced. llvm-svn: 285201
* LegalizeDAG: Support promoting [US]DIV and [US]REM operationsTom Stellard2016-10-261-1/+18
| | | | | | | | | | | | | | | | | | Summary: AMDGPU will need this one i16 is added as a legal type. This is tested by: test/CodeGen/AMDGPU/sdiv.ll test/CodeGen/AMDGPU/sdivrem24.ll test/CodeGen/AMDGPU/udiv.ll test/CodeGen/AMDGPU/udivrem24.ll Reviewers: bogner, efriedma Subscribers: efriedma, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D25699 llvm-svn: 285199
* DebugInfo: support for DWARFv5 DW_AT_alignment attributeVictor Leschuk2016-10-262-1/+24
| | | | | | | | | | | | * Assume that clang passes non-zero alignment value to DIBuilder only in case when it was forced by C++11 'alignas', C11 '_Alignas' or compiler attribute '__attribute__((aligned (N)))'. * Emit DW_AT_alignment if alignment is specified for type/object. Differential Revision: https://reviews.llvm.org/D24425 llvm-svn: 285189
* Revert r285181 "DebugInfo: support for DWARFv5 DW_AT_alignment attribute".Vassil Vassilev2016-10-262-24/+1
| | | | | | The commit broke the builds. llvm-svn: 285183
* DebugInfo: support for DWARFv5 DW_AT_alignment attributeVictor Leschuk2016-10-262-1/+24
| | | | | | | | | | | | * Assume that clang passes non-zero alignment value to DIBuilder only in case when it was forced by C++11 'alignas', C11 '_Alignas' or compiler attribute '__attribute__((aligned (N)))'. * Emit DW_AT_alignment if alignment is specified for type/object. Differential Revision: https://reviews.llvm.org/D24425 llvm-svn: 285181
* [codeview] support emitting indirect virtual base class informationBob Haarman2016-10-251-1/+4
| | | | | | | | | | | | | | | | Summary: Fixes PR28281. MSVC lists indirect virtual base classes in the field list of a class, using LF_IVBCLASS records. This change makes LLVM emit such records when processing DW_TAG_inheritance tags with the DIFlagVirtual and (newly introduced) DIFlagIndirect tags. Reviewers: rnk, ruiu, zturner Differential Revision: https://reviews.llvm.org/D25578 llvm-svn: 285130
* [DAGCombiner] Enable (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), ↵Simon Pilgrim2016-10-251-3/+3
| | | | | | -1)) combine for splatted vectors llvm-svn: 285129
* [DAGCombiner] Enable srem(x.y) -> urem(x,y) combine for vectorsSimon Pilgrim2016-10-251-4/+2
| | | | | | SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927 llvm-svn: 285123
* [DAGCombiner] Enable sdiv(x.y) -> udiv(x,y) combine for vectorsSimon Pilgrim2016-10-251-4/+2
| | | | | | SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927 llvm-svn: 285118
* revert: "Remove debug location from common tail when tail-merging"Robert Lougher2016-10-251-5/+2
| | | | | | | | This reverts r285093, as it caused unexpected buildbot failures on clang-ppc64le-linux, clang-ppc64be-linux, clang-ppc64be-linux-multistage and clang-ppc64be-linux-lnt. Failing test ubsan/TestCases/TypeCheck/vptr.cpp. llvm-svn: 285110
* Add option to specify minimum number of entries for jump tablesEvandro Menezes2016-10-251-3/+14
| | | | | | | | | | Add an option to allow easier experimentation by target maintainers with the minimum number of entries to create jump tables. Also clarify the name of the other existing option governing the creation of jump tables. Differential revision: https://reviews.llvm.org/D25883 llvm-svn: 285104
* Switch lowering: improve partitioning of jump tablesEvandro Menezes2016-10-251-14/+31
| | | | | | | | | | | When there's a tie between partitionings of jump tables, consider also cases that result in no jump tables, but in one or a few cases. The motivation is that many contemporary processors typically perform case switches fairly quickly. Differential revision: https://reviews.llvm.org/D25212 llvm-svn: 285099
* Remove debug location from common tail when tail-mergingRobert Lougher2016-10-251-2/+5
| | | | | | | | | | | | | | The branch folding pass tail merges blocks into a common-tail. However, the tail retains the debug information from one of the original inputs to the merge (chosen randomly). This is a problem for sampled-based PGO, as hits on the common-tail will be attributed to whichever block was chosen, irrespective of which path was actually taken to the common-tail. This patch fixes the issue by nulling the debug location for the common-tail. Differential Revision: https://reviews.llvm.org/D25742 llvm-svn: 285093
* [DAGCombine] Preserve shuffles when one of the vector operands is constantZvi Rackover2016-10-251-34/+75
| | | | | | | | | | | | | | | | | | | | Summary: Do *not* perform combines such as: vector_shuffle<4,1,2,3>(build_vector(Ud, C0, C1 C2), scalar_to_vector(X)) -> build_vector(X, C0, C1, C2) Keeping the shuffle allows lowering the constant build_vector to a materialized constant vector (such as a vector-load from the constant-pool or some other idiom). Reviewers: delena, igorb, spatel, mkuper, andreadb, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25524 llvm-svn: 285063
* MachineInstrBundle: Pass iterators to getBundle(Start|End); NFCMatthias Braun2016-10-251-2/+2
| | | | | | | | This is a function to go backwards in a block to find the first instruction in a bundle, so iterator is a more natural choice for parameter/return rather than a reference to a MachineInstruction. llvm-svn: 285051
* CodeGen/Passes: Pass MachineFunction as functor arg; NFCMatthias Braun2016-10-242-9/+10
| | | | | | | | Passing a MachineFunction as argument is more natural and avoids an unnecessary round-trip through the logic determining the correct Subtarget because MachineFunction already has a reference anyway. llvm-svn: 285039
* [SelectionDAG] Update ComputeNumSignBits SRA/SHL handlers to accept scalar ↵Simon Pilgrim2016-10-241-6/+7
| | | | | | | | | | or vector splats Use isConstOrConstSplat helper. Also use APInt instead of getZExtValue directly to avoid out of range issues. llvm-svn: 285033
* Use MachineInstr::mop_iterator instead of MIOperands; NFCMatthias Braun2016-10-241-6/+6
| | | | | | | | (Const)?MIOperands is equivalent to the C++ style MachineInstr::mop_iterator. Use the latter for consistency except for a few callers of MIOperands::analyzePhysReg(). llvm-svn: 285029
* Use SDValue::getConstantOperandVal() helper. NFCI.Simon Pilgrim2016-10-241-4/+2
| | | | llvm-svn: 285025
* Target: Change various section classifiers in TargetLoweringObjectFile to ↵Peter Collingbourne2016-10-241-45/+48
| | | | | | | | | | | | | | | | take a GlobalObject. These functions are about classifying a global which will actually be emitted, so it does not make sense for them to take a GlobalValue which may for example be an alias. Change the Mach-O object writer and the Hexagon, Lanai and MIPS backends to look through aliases before using TargetLoweringObjectFile interfaces. These are functional changes but all appear to be bug fixes. Differential Revision: https://reviews.llvm.org/D25917 llvm-svn: 285006
* CodeGen: Do not add a global's address space to the folding set profile.Peter Collingbourne2016-10-241-2/+0
| | | | | | | It is already part of the type (which is part of the global, which is already being added), so there's no need to do it. llvm-svn: 285002
* [DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constantSanjay Patel2016-10-231-43/+32
| | | | llvm-svn: 284953
* Use SDValue::getConstantOperandVal() helper. NFCI.Simon Pilgrim2016-10-231-4/+1
| | | | llvm-svn: 284949
* Remove LLVM_CONSTEXPR.Justin Lebar2016-10-231-2/+1
| | | | | | | | | | | | Summary: With MSVC 2013 and GCC < 4.8 gone, we can use the "constexpr" keyword. Reviewers: bkramer, mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25901 llvm-svn: 284947
* [DAG] enhance computeKnownBits to handle SHL with vector splat constantSanjay Patel2016-10-211-10/+9
| | | | | | Also, use APInt to avoid crashing on types larger than vNi64. llvm-svn: 284874
* [DAG] fold negation of sign-bitSanjay Patel2016-10-211-11/+27
| | | | | | | | | | | | | | | | 0 - X --> 0, if the sub is NUW 0 - X --> 0, if X is 0 or the minimum signed value and the sub is NSW 0 - X --> X, if X is 0 or the minimum signed value This is the DAG equivalent of: https://reviews.llvm.org/rL284649 plus the fold for the NUW case which already existed in InstSimplify. Note that we miss a vector fold because of a deficiency in the DAG version of computeKnownBits(). llvm-svn: 284844
* fix variable names; NFCISanjay Patel2016-10-211-2/+2
| | | | | | | | Because we're just 'or-ing' these 2 variables later in the code, I don't think there's a logical bug here, but of course the string with "no size" is the one that should have the size suffix stripped off. llvm-svn: 284826
* [DAG] use SDNode flags 'nsz' to enable fadd/fsub with zero foldsSanjay Patel2016-10-211-16/+20
| | | | | | | | | | | | | | | | | | | | | As discussed in D24815, let's start the process of killing off the broken fast-math global state housed in TargetOptions and eliminate the need for function-level fast-math attributes. Here we enable two similar folds that are possible when we don't care about signed-zero: fadd nsz x, 0 --> x fsub nsz 0, x --> -x Note that although the test cases include a 'sin' function call, I'm side-stepping the FMF-on-calls question (and lack of support in the DAG) for now. It's not needed for these tests - isNegatibleForFree/GetNegatedExpression just look through a ISD::FSIN node. Also, when we create an FNEG node and propagate the Flags of the FSUB to it, this doesn't actually do anything today because Flags are silently dropped for any node that is not a binary operator. Differential Revision: https://reviews.llvm.org/D25297 llvm-svn: 284824
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