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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-10-25 21:20:18 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-10-25 21:20:18 +0000 |
| commit | f534573e8c906b9375c8d65f9881918955719cf8 (patch) | |
| tree | fcb25f284d11d7da032ba11782e2f5b6ffbe85d7 /llvm/lib/CodeGen | |
| parent | 03a88ccba340bd7a7c83b988443a144de09c91a6 (diff) | |
| download | bcm5719-llvm-f534573e8c906b9375c8d65f9881918955719cf8.tar.gz bcm5719-llvm-f534573e8c906b9375c8d65f9881918955719cf8.zip | |
[DAGCombiner] Enable srem(x.y) -> urem(x,y) combine for vectors
SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927
llvm-svn: 285123
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index daa0ea7afbd..f8953f0fb49 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2471,10 +2471,8 @@ SDValue DAGCombiner::visitREM(SDNode *N) { if (isSigned) { // If we know the sign bits of both operands are zero, strength reduce to a // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 - if (!VT.isVector()) { - if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) - return DAG.getNode(ISD::UREM, DL, VT, N0, N1); - } + if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) + return DAG.getNode(ISD::UREM, DL, VT, N0, N1); } else { // fold (urem x, pow2) -> (and x, pow2-1) if (N1C && !N1C->isNullValue() && !N1C->isOpaque() && |
