summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Expand)AuthorAgeFilesLines
* [AArch64] -fpatchable-function-entry=N,0: place patch label after BTIFangrui Song2020-02-031-1/+7
* Revert "Reland: [DWARF] Allow cross-CU references of subprogram definitions"Vedant Kumar2020-01-294-28/+12
* [GlobalMerge] Preserve symbol visibility when merging globalsMichael Spang2020-01-291-0/+2
* Reland "[StackColoring] Remap PseudoSourceValue frame indices via MachineFunc...Fangrui Song2020-01-271-7/+9
* [PatchableFunction] Allow empty entry MachineBasicBlockFangrui Song2020-01-241-3/+8
* Add function attribute "patchable-function-prefix" to support -fpatchable-fun...Fangrui Song2020-01-241-4/+29
* [AsmPrinter] Don't emit __patchable_function_entries entry if "patchable-func...Fangrui Song2020-01-241-1/+5
* [CodeGen] Move fentry-insert, xray-instrumentation and patchable-function bef...Fangrui Song2020-01-241-6/+6
* [PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst.Hiroshi Yamauchi2020-01-231-0/+1
* [StackColoring] Remap FixedStackPseudoSourceValue frame index referenced by M...Fangrui Song2020-01-211-0/+19
* RegisterClassInfo::computePSetLimit - assert that we actually find a register.Simon Pilgrim2020-01-151-0/+1
* [Scheduler] Adjust interface of CreateTargetMIHazardRecognizer to use Schedul...David Green2020-01-151-3/+3
* [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.Michael Liao2020-01-141-0/+9
* [DAGCombine] Replace `getIntPtrConstant()` with `getVectorIdxTy()`.Michael Liao2020-01-141-1/+2
* [LegalizeTypes] Remove untested code from ExpandIntOp_UINT_TO_FPCraig Topper2020-01-141-70/+2
* [MachineScheduler] Reduce reordering due to mem op clusteringJay Foad2020-01-141-0/+2
* [AIX][XCOFF] Supporting the ReadOnlyWithRel SectionKnddiggerlin2020-01-141-1/+4
* [FPEnv] Fix chain handling regression after 04a8696Ulrich Weigand2020-01-142-34/+31
* Make helper functions static or move them into anonymous namespaces. NFC.Benjamin Kramer2020-01-141-2/+2
* Fix "MIParser::getIRValue(unsigned int)’ defined but not used" warning. NFCI.Simon Pilgrim2020-01-141-6/+0
* [SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() ...Simon Pilgrim2020-01-141-11/+12
* [SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() ...Simon Pilgrim2020-01-141-10/+12
* [GlobalISel] Change representation of shuffle masks in MachineOperand.Eli Friedman2020-01-137-47/+24
* Revert "[DWARF5][DebugInfo]: Added support for DebugInfo generation for auto ...Amy Huang2020-01-131-8/+0
* [LegalizeIntegerTypes][X86] Add support for expanding input of STRICT_SINT_TO...Craig Topper2020-01-131-6/+30
* Rework be15dfa88fb1 such that it works with GlobalISel which doesn't use EVTDaniel Sanders2020-01-131-3/+11
* [llvm][MIRVRegNamerUtils] Adding hashing on FrameIndex MachineOperands.Puyan Lotfi2020-01-131-1/+2
* [SelectionDAG] ComputeNumSignBits add getValidMaximumShiftAmountConstant() fo...Simon Pilgrim2020-01-131-0/+31
* [LegalizeTypes] Add SoftenFloatResult support for STRICT_SINT_TO_FP/STRICT_UI...Andrew Wei2020-01-141-8/+16
* [SelectionDAG] ComputeNumSignBits add getValidMinimumShiftAmountConstant() IS...Simon Pilgrim2020-01-131-1/+4
* [Scheduler] Remove superfluous casts. NFCDavid Green2020-01-131-4/+2
* [SelectionDAG] ComputeNumSignBits - Use getValidShiftAmountConstant for shift...Simon Pilgrim2020-01-131-15/+8
* [SelectionDAG] ComputeKnownBits - Add DemandedElts support to getValidShiftAm...Simon Pilgrim2020-01-131-8/+14
* [FPEnv] Fix chain handling for fpexcept.strict nodesUlrich Weigand2020-01-132-14/+81
* [SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant() ISD:...Simon Pilgrim2020-01-131-0/+3
* [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/...Simon Pilgrim2020-01-131-0/+11
* [DWARF5][DebugInfo]: Added support for DebugInfo generation for auto return t...Awanish Pandey2020-01-131-0/+8
* __patchable_function_entries: don't use linkage field 'unique' with -no-integ...Fangrui Song2020-01-121-18/+21
* [NFC] Refactor memory ops cluster methodQiu Chaofan2020-01-121-14/+7
* [LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UINT_TO_FLOAT legali...Craig Topper2020-01-111-3/+6
* [TargetLowering][X86] Connect the chain from STRICT_FSETCC in TargetLowering:...Craig Topper2020-01-111-3/+5
* [LegalizeVectorOps] Expand vector MERGE_VALUES immediately.Craig Topper2020-01-111-0/+11
* [LegalizeVectorOps] Remove some of the simpler Expand methods. Pass Results v...Craig Topper2020-01-111-125/+77
* [LegalizeVectorOps] Only pass SDNode* instead SDValue to all of the Expand* a...Craig Topper2020-01-111-251/+251
* moveOperands - assert Src/Dst MachineOperands are non-null.Simon Pilgrim2020-01-111-1/+1
* [TargetLowering][ARM][Mips][WebAssembly] Remove the ordered FP compare from R...Craig Topper2020-01-102-10/+3
* Let targets adjust operand latency of bundlesStanislav Mekhanoshin2020-01-101-1/+6
* [TargetLowering] Use SelectionDAG::getSetCC and remove a repeated call to get...Craig Topper2020-01-101-8/+4
* [TargetLowering][ARM][X86] Change softenSetCCOperands handling of ONE to avoi...Craig Topper2020-01-101-10/+9
* [LegalizeVectorOps] Improve handling of multi-result operations.Craig Topper2020-01-101-173/+271
OpenPOWER on IntegriCloud