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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-13 12:01:56 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-13 12:02:13 +0000 |
| commit | ef5debac4302cd479ddd9e784a5b5acc8c2b9804 (patch) | |
| tree | a828faa45be45750af04ec1b30531ca2c9792e91 /llvm/lib/CodeGen | |
| parent | 7efc7ca8edf6762dc64472417dabfbbdd838ceeb (diff) | |
| download | bcm5719-llvm-ef5debac4302cd479ddd9e784a5b5acc8c2b9804.tar.gz bcm5719-llvm-ef5debac4302cd479ddd9e784a5b5acc8c2b9804.zip | |
[SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant() ISD::SHL support
As mentioned on D72573
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 4fa438a2795..59180597130 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2834,6 +2834,9 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts, Known.One <<= Shift; // Low bits are known zero. Known.Zero.setLowBits(Shift); + } else if (const APInt *ShMinAmt = getValidMinimumShiftAmountConstant(Op)) { + // Minimum shift low bits are known zero. + Known.Zero.setLowBits(ShMinAmt->getZExtValue()); } else { // No matter the shift amount, the trailing zeros will stay zero. Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); |
