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path: root/llvm/lib/CodeGen/VirtRegRewriter.cpp
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* Fix a bunch of namespace pollution.Dan Gohman2009-08-071-2/+16
| | | | llvm-svn: 78363
* Add reload and remat backscheduling. This is disabled by default. UseDavid Greene2009-07-281-26/+150
| | | | | | -schedule-spills=true to enable. llvm-svn: 77327
* More migration to raw_ostream, the water has dried up around the iostream hole.Daniel Dunbar2009-07-251-5/+7
| | | | | | | | | | - Some clients which used DOUT have moved to DEBUG. We are deprecating the "magic" DOUT behavior which avoided calling printing functions when the statement was disabled. In addition to being unnecessary magic, it had the downside of leaving code in -Asserts builds, and of hiding potentially unnecessary computations. llvm-svn: 77019
* Let each target determines whether a machine instruction is dead. If true, ↵Evan Cheng2009-07-221-25/+2
| | | | | | | | that allows late codeine passes to delete it. This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround. llvm-svn: 76703
* Another rewriter bug exposed by recent coalescer changes. ↵Evan Cheng2009-07-211-23/+27
| | | | | | ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past. llvm-svn: 76558
* Enable cross register class coalescing.Evan Cheng2009-07-181-4/+35
| | | | llvm-svn: 76281
* Fix my brain cramp by inverting the assertion condition.Evan Cheng2009-07-171-3/+1
| | | | llvm-svn: 76131
* Disable this assert for now, it is firing on an llvm-gcc bootstrap. :(Daniel Dunbar2009-07-161-0/+2
| | | | llvm-svn: 76123
* Fix inverted preprocessor conditional.Daniel Dunbar2009-07-161-1/+1
| | | | llvm-svn: 76111
* Changed my mind. We now allow remat of instructions whose defs have subreg ↵Evan Cheng2009-07-161-1/+8
| | | | | | indices. llvm-svn: 76100
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-1/+1
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-4/+4
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-4/+5
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Remove TargetInstrInfo::CommuteChangesDestination and added ↵Evan Cheng2009-07-101-1/+27
| | | | | | findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements. llvm-svn: 75264
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves ↵Evan Cheng2009-07-011-2/+6
| | | | | | the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. llvm-svn: 74580
* Add a bit IsUndef to MachineOperand. This indicates the def / use register ↵Evan Cheng2009-06-301-26/+22
| | | | | | | | | | operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing. This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def. llvm-svn: 74518
* Removed SimpleRewriter.Lang Hames2009-06-041-82/+2
| | | | llvm-svn: 72880
* Fix for PR4225: When rewriter reuse a value in a physical register , it ↵Evan Cheng2009-06-031-5/+19
| | | | | | clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well. llvm-svn: 72758
* Update to in-place spilling framework. Includes live interval scaling and ↵Lang Hames2009-06-021-3/+42
| | | | | | trivial rewriter. llvm-svn: 72729
* Fix PR4210. Rewritter should track and update kills of sub-registers as well.Evan Cheng2009-05-151-42/+63
| | | | llvm-svn: 71848
* Teach TransferDeadness to delete truly dead instructions if they do not ↵Evan Cheng2009-05-121-13/+37
| | | | | | produce side effects. llvm-svn: 71606
* Renamed Spiller classes (plus uses and related files) to VirtRegRewriter.Lang Hames2009-05-061-0/+2141
llvm-svn: 71057
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