| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [SelectionDAG] computeKnownBits - early-out if any BUILD_VECTOR element has n... | Simon Pilgrim | 2016-10-28 | 1 | -0/+4 |
| * | [SelectionDAG] Tidyup UDIV computeKnownBits implementation | Simon Pilgrim | 2016-10-28 | 1 | -2/+0 |
| * | [SelectionDAG] Increment computeKnownBits recursion depth for SMIN/SMAX/UMIN/... | Simon Pilgrim | 2016-10-28 | 1 | -2/+2 |
| * | Revert "[DAGCombiner] Add vector demanded elements support to computeKnownBits" | Juergen Ributzka | 2016-10-28 | 1 | -111/+13 |
| * | [DAGCombiner] Add vector demanded elements support to computeKnownBits | Simon Pilgrim | 2016-10-27 | 1 | -13/+111 |
| * | Do not assume that FP vector operands are never legalized by expanding | Nemanja Ivanovic | 2016-10-26 | 1 | -1/+2 |
| * | LegalizeDAG: Support promoting [US]DIV and [US]REM operations | Tom Stellard | 2016-10-26 | 1 | -1/+18 |
| * | [DAGCombiner] Enable (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -... | Simon Pilgrim | 2016-10-25 | 1 | -3/+3 |
| * | [DAGCombiner] Enable srem(x.y) -> urem(x,y) combine for vectors | Simon Pilgrim | 2016-10-25 | 1 | -4/+2 |
| * | [DAGCombiner] Enable sdiv(x.y) -> udiv(x,y) combine for vectors | Simon Pilgrim | 2016-10-25 | 1 | -4/+2 |
| * | Switch lowering: improve partitioning of jump tables | Evandro Menezes | 2016-10-25 | 1 | -14/+31 |
| * | [DAGCombine] Preserve shuffles when one of the vector operands is constant | Zvi Rackover | 2016-10-25 | 1 | -34/+75 |
| * | [SelectionDAG] Update ComputeNumSignBits SRA/SHL handlers to accept scalar or... | Simon Pilgrim | 2016-10-24 | 1 | -6/+7 |
| * | Use SDValue::getConstantOperandVal() helper. NFCI. | Simon Pilgrim | 2016-10-24 | 1 | -4/+2 |
| * | CodeGen: Do not add a global's address space to the folding set profile. | Peter Collingbourne | 2016-10-24 | 1 | -2/+0 |
| * | [DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constant | Sanjay Patel | 2016-10-23 | 1 | -43/+32 |
| * | Use SDValue::getConstantOperandVal() helper. NFCI. | Simon Pilgrim | 2016-10-23 | 1 | -4/+1 |
| * | [DAG] enhance computeKnownBits to handle SHL with vector splat constant | Sanjay Patel | 2016-10-21 | 1 | -10/+9 |
| * | [DAG] fold negation of sign-bit | Sanjay Patel | 2016-10-21 | 1 | -11/+27 |
| * | [DAG] use SDNode flags 'nsz' to enable fadd/fsub with zero folds | Sanjay Patel | 2016-10-21 | 1 | -16/+20 |
| * | Fix *_EXTEND_VECTOR_INREG legalization | Pirama Arumuga Nainar | 2016-10-20 | 1 | -3/+19 |
| * | [Target] remove TargetRecip class; 2nd try | Sanjay Patel | 2016-10-20 | 1 | -11/+34 |
| * | [DAGCombiner] Add general constant vector support to (srl (shl x, c), c) -> (... | Simon Pilgrim | 2016-10-20 | 1 | -8/+8 |
| * | Merged nested ifs. NFCI. | Simon Pilgrim | 2016-10-19 | 1 | -7/+6 |
| * | [DAGCombiner] Add general constant vector support to (shl (add x, c1), c2) ->... | Simon Pilgrim | 2016-10-19 | 1 | -4/+5 |
| * | [WinEH] Allow catchpads to reuse the same catch object | Reid Kleckner | 2016-10-19 | 1 | -4/+7 |
| * | [DAG] optimize negation of bool | Sanjay Patel | 2016-10-19 | 1 | -2/+19 |
| * | [DAGCombiner] Add general constant vector support to (shl (sra x, c1), c1) ->... | Simon Pilgrim | 2016-10-19 | 1 | -7/+6 |
| * | [DAGCombiner] Add general constant vector support to (shl (mul x, c1), c2) ->... | Simon Pilgrim | 2016-10-19 | 1 | -5/+6 |
| * | [DAGCombiner] Just call isConstOrConstSplat directly. NFCI. | Simon Pilgrim | 2016-10-19 | 1 | -8/+4 |
| * | [DAGCombine] Generalize distributeTruncateThroughAnd to work with any non-opa... | Simon Pilgrim | 2016-10-19 | 1 | -13/+9 |
| * | revert r284495: [Target] remove TargetRecip class | Sanjay Patel | 2016-10-18 | 1 | -32/+9 |
| * | [Target] remove TargetRecip class; move reciprocal estimate isel functionalit... | Sanjay Patel | 2016-10-18 | 1 | -9/+32 |
| * | [DAGCombiner] Add splatted vector support to (udiv x, (shl pow2, y)) -> x >>u... | Simon Pilgrim | 2016-10-18 | 1 | -2/+3 |
| * | Strip trailing whitespace (NFCI) | Simon Pilgrim | 2016-10-18 | 1 | -1/+1 |
| * | [DAG] use isConstOrConstSplat in ComputeNumSignBits to optimize SRA | Sanjay Patel | 2016-10-17 | 1 | -1/+1 |
| * | [DAG] make isConstOrConstSplat and isConstOrConstSplatFP more accessible; NFC | Sanjay Patel | 2016-10-17 | 2 | -38/+34 |
| * | [DAG] optimize away an arithmetic-right-shift of a 0 or -1 value | Sanjay Patel | 2016-10-17 | 1 | -0/+4 |
| * | [SDAG] Use ABI type alignment for constant pools when optimizing for size | James Molloy | 2016-10-17 | 1 | -1/+3 |
| * | [MachineMemOperand] Move synchronization scope and atomic orderings from SDNo... | Konstantin Zhuravlyov | 2016-10-15 | 4 | -65/+29 |
| * | [DAG] avoid creating illegal node when transforming negated shifted sign bit | Sanjay Patel | 2016-10-14 | 1 | -2/+3 |
| * | TargetLowering: Add SimplifyDemandedBits() helper to TargetLoweringOpt | Tom Stellard | 2016-10-14 | 1 | -2/+55 |
| * | [DAG] add folds for negated shifted sign bit | Sanjay Patel | 2016-10-14 | 1 | -0/+13 |
| * | Fix use-after-frees | Nicolai Haehnle | 2016-10-14 | 1 | -2/+2 |
| * | [DAGCombiner] Teach createBuildVecShuffle to handle cases where input vectors... | Craig Topper | 2016-10-14 | 1 | -5/+9 |
| * | [DAG] hoist DL(N) and fix formatting; NFC | Sanjay Patel | 2016-10-13 | 1 | -24/+31 |
| * | LegalizeDAG: Implement PROMOTE for ISD::BITREVERSE | Tom Stellard | 2016-10-13 | 1 | -1/+2 |
| * | Revert "In visitSTORE, always use FindBetterChain, rather than only when UseA... | Nirav Dave | 2016-10-13 | 1 | -120/+271 |
| * | In visitSTORE, always use FindBetterChain, rather than only when UseAA is ena... | Nirav Dave | 2016-10-13 | 1 | -271/+120 |
| * | [DAGCombiner] Add vector support to (mul (shl X, Y), Z) -> (shl (mul X, Z), Y... | Simon Pilgrim | 2016-10-13 | 1 | -7/+6 |
