summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Revert "Revert "Add Constant Hoisting Pass" (r200034)"Juergen Ributzka2014-01-251-6/+12
| | | | | | | This reverts commit r200058 and adds the using directive for ARMTargetTransformInfo to silence two g++ overload warnings. llvm-svn: 200062
* Revert "Add Constant Hoisting Pass" (r200034)Hans Wennborg2014-01-251-12/+6
| | | | | | | | | | | | | | | This commit caused -Woverloaded-virtual warnings. The two new TargetTransformInfo::getIntImmCost functions were only added to the superclass, and to the X86 subclass. The other targets were not updated, and the warning highlighted this by pointing out that e.g. ARMTTI::getIntImmCost was hiding the two new getIntImmCost variants. We could pacify the warning by adding "using TargetTransformInfo::getIntImmCost" to the various subclasses, or turning it off, but I suspect that it's wrong to leave the functions unimplemnted in those targets. The default implementations return TCC_Free, which I don't think is right e.g. for ARM. llvm-svn: 200058
* Add Constant Hoisting PassJuergen Ributzka2014-01-241-6/+12
| | | | | | | | Retry commit r200022 with a fix for the build bot errors. Constant expressions have (unlike instructions) module scope use lists and therefore may have users in different functions. The fix is to simply ignore these out-of-function uses. llvm-svn: 200034
* Revert "Add Constant Hoisting Pass"Juergen Ributzka2014-01-241-12/+6
| | | | | | This reverts commit r200022 to unbreak the build bots. llvm-svn: 200024
* Add Constant Hoisting PassJuergen Ributzka2014-01-241-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass identifies expensive constants to hoist and coalesces them to better prepare it for SelectionDAG-based code generation. This works around the limitations of the basic-block-at-a-time approach. First it scans all instructions for integer constants and calculates its cost. If the constant can be folded into the instruction (the cost is TCC_Free) or the cost is just a simple operation (TCC_BASIC), then we don't consider it expensive and leave it alone. This is the default behavior and the default implementation of getIntImmCost will always return TCC_Free. If the cost is more than TCC_BASIC, then the integer constant can't be folded into the instruction and it might be beneficial to hoist the constant. Similar constants are coalesced to reduce register pressure and materialization code. When a constant is hoisted, it is also hidden behind a bitcast to force it to be live-out of the basic block. Otherwise the constant would be just duplicated and each basic block would have its own copy in the SelectionDAG. The SelectionDAG recognizes such constants as opaque and doesn't perform certain transformations on them, which would create a new expensive constant. This optimization is only applied to integer constants in instructions and simple (this means not nested) constant cast experessions. For example: %0 = load i64* inttoptr (i64 big_constant to i64*) Reviewed by Eric llvm-svn: 200022
* Revert r162101 and replace it with a solution that works for targets where ↵Owen Anderson2014-01-221-3/+3
| | | | | | | | | | the pointer type is illegal. This is a horrible bit of code. We're calling a simplification routine *in the middle* of type legalization. We tell the simplification routine that it's running after legalization, but some of the types it will encounter will be illegal! The fix is only to invoke the simplification if the types in question were legal, so that none of its invariants will be violated. llvm-svn: 199847
* Refactor function that checks that __builtin_returnaddress's argument is ↵Bill Wendling2014-01-061-0/+12
| | | | | | | | | constant. This moves the check up into the parent class so that all targets can use it without having to copy (and keep in sync) the same error message. llvm-svn: 198579
* Lower stackmap intrinsics directly to their target opcode in the DAG builder.Andrew Trick2013-10-311-0/+13
| | | | llvm-svn: 193769
* Replace sra with srl if a single sign bit is requiredRichard Sandiford2013-10-171-3/+14
| | | | | | E.g. (and (sra (i32 x) 31) 2) -> (and (srl (i32 x) 30) 2). llvm-svn: 192884
* Handle (shl (anyext (shr ...))) in SimpilfyDemandedBitsRichard Sandiford2013-10-161-0/+25
| | | | | | | | | | This is really an extension of the current (shl (shr ...)) -> shl optimization. The main difference is that certain upper bits must also not be demanded. The motivating examples are the first two in the testcase, which occur in llvmpipe output. llvm-svn: 192783
* TargetLowering: Don't index into empty string.Will Dietz2013-10-131-1/+1
| | | | | | (This is triggered by current lit tests) llvm-svn: 192549
* Use getPointerSizeInBits() rather than 8 * getPointerSize()Matt Arsenault2013-10-101-2/+3
| | | | llvm-svn: 192386
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-281-7/+18
| | | | | | | | | | | | This is useful for targets like R600, which only support GT, GE, NE, and EQ condition codes as it removes the need to handle unsupported condition codes in target specific code. There are no tests with this commit, but R600 has been updated to take advantage of this new feature, so its existing selectcc tests are now testing the swapped operands path. llvm-svn: 191601
* Add missing check to SETCC optimization.Eli Friedman2013-09-241-0/+1
| | | | | | PR17338. llvm-svn: 191337
* SelectionDAG: create correct BooleanContent constantsTim Northover2013-09-061-1/+5
| | | | | | | | | | | | | | | Occasionally DAGCombiner can spot that a SETCC operation is completely redundant and reduce it to "all true" or "all false". If this happens to a vector, the value produced has to take account of what a normal comparison would have produced, which may be an all-1s bitmask. The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when triggered so there are no tests. However, I believe it's still clearly the right change and may save someone else some hassle if it suddenly becomes reachable. So I'm doing it anyway. llvm-svn: 190147
* Update makeLibCall to return both the call and the chain associated with the ↵Michael Gottesman2013-08-131-11/+14
| | | | | | | | | | | | | | | libcall instead of just the call. This allows us to specify libcalls that return void. LowerCallTo returns a pair with the return value of the call as the first element and the chain associated with the return value as the second element. If we lower a call that has a void return value, LowerCallTo returns an SDValue with a NULL SDNode and the chain for the call. Thus makeLibCall by just returning the first value makes it impossible for you to set up the chain so that the call is not eliminated as dead code. I also updated all references to makeLibCall to reflect the new return type. llvm-svn: 188300
* Remove trailing whitespace from SelectionDAG/*.cppStephen Lin2013-07-081-1/+1
| | | | llvm-svn: 185780
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-221-1/+1
| | | | llvm-svn: 184642
* TargetLowering: Clean up method description commentsDavid Majnemer2013-06-081-3/+3
| | | | llvm-svn: 183623
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-10/+10
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & ↵Benjamin Kramer2013-05-211-1/+2
| | | | | | | | 0) == 0. Fixes PR16083. llvm-svn: 182357
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-181-2/+4
| | | | llvm-svn: 182180
* DAGCombine: Also shrink eq compares where the constant is exactly as large ↵Benjamin Kramer2013-05-161-1/+1
| | | | | | | | | | | | as the smaller type. if ((x & 255) == 255) before: movzbl %al, %eax cmpl $255, %eax after: cmpb $-1, %al llvm-svn: 182038
* Add static cast to unsigned char whenever a character classification ↵Guy Benyei2013-02-121-1/+1
| | | | | | function is called with a signed char argument, in order to avoid assertions in Windows Debug configuration. llvm-svn: 175006
* Use AttributeSet accessor methods instead of Attribute accessor methods.Bill Wendling2013-01-181-4/+4
| | | | | | | Further encapsulation of the Attribute object. Don't allow direct access to the Attribute object as an aggregate. llvm-svn: 172853
* Remove some accidentaly duplicated code. This needs urgent cleanup :(Benjamin Kramer2013-01-111-270/+0
| | | | llvm-svn: 172248
* Split TargetLowering into a CodeGen and a SelectionDAG part.Benjamin Kramer2013-01-111-971/+5
| | | | | | | | | This fixes some of the cycles between libCodeGen and libSelectionDAG. It's still a complete mess but as long as the edges consist of virtual call it doesn't cause breakage. BasicTTI did static calls and thus broke some build configurations. llvm-svn: 172246
* For inline asm:Eric Christopher2013-01-111-3/+7
| | | | | | | | | | | - recognize string "{memory}" in the MI generation - mark as mayload/maystore when there's a memory clobber constraint. PR14859. Patch by Krzysztof Parzyszek llvm-svn: 172228
* Refactor to expose RTLIB calls to targets.Tim Northover2013-01-091-0/+155
| | | | | | | | | | fp128 is almost but not quite completely illegal as a type on AArch64. As a result it needs to have a register class (for argument passing mainly), but all operations need to be lowered to runtime calls. Currently there's no way for targets to do this (without duplicating code), as the relevant functions are hidden in SelectionDAG. This patch changes that. llvm-svn: 171971
* Add fp128 rtlib function names to LLVMTim Northover2013-01-081-0/+100
| | | | llvm-svn: 171867
* Switch TargetTransformInfo from an immutable analysis pass that requiresChandler Carruth2013-01-071-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. llvm-svn: 171681
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-3/+3
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Remove the Function::getRetAttributes method in favor of using the ↵Bill Wendling2012-12-301-6/+6
| | | | | | AttributeSet accessor method. llvm-svn: 171256
* Change AsmOperandInfo::ConstraintVT to MVT, instead of EVT.Patrik Hagglund2012-12-191-4/+4
| | | | | | Accordingly, add MVT::getVT. llvm-svn: 170550
* Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund2012-12-191-9/+10
| | | | | | from EVT. llvm-svn: 170536
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-191-4/+4
| | | | | | EVTs. llvm-svn: 170535
* Change TargetLowering::TransformToType to contain MVTs, instead ofPatrik Hagglund2012-12-191-4/+4
| | | | | | EVTs. llvm-svn: 170534
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-191-2/+2
| | | | | | of EVT. llvm-svn: 170532
* Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund2012-12-191-9/+9
| | | | llvm-svn: 170524
* Change TargetLowering::getCondCodeAction to take an MVT, instead ofPatrik Hagglund2012-12-191-2/+2
| | | | | | EVT. llvm-svn: 170522
* After reducing the size of an operation in the DAG we zero-extend the reducedNadav Rotem2012-12-191-2/+5
| | | | | | | | bitwidth op back to the original size. If we reduce ANDs then this can cause an endless loop. This patch changes the ZEXT to ANY_EXTEND if the demanded bits are equal or smaller than the size of the reduced operation. llvm-svn: 170505
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-191-6/+6
| | | | | | single attribute in the future. llvm-svn: 170502
* Remove more of 'else's after 'returns'. No functional change.Craig Topper2012-12-191-6/+6
| | | | llvm-svn: 170497
* Remove a bunch of 'else's after 'returns'Craig Topper2012-12-191-18/+18
| | | | llvm-svn: 170496
* Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be ↵Craig Topper2012-12-191-3/+9
| | | | | | rewritten as a compare against a constant 0 with the opposite condition. llvm-svn: 170495
* Check multiple register classes for inline asm tied registersHal Finkel2012-12-181-3/+16
| | | | | | | | | | | | | | | | | | A register can be associated with several distinct register classes. For example, on PPC, the floating point registers are each associated with both F4RC (which holds f32) and F8RC (which holds f64). As a result, this code would fail when provided with a floating point register and an f64 operand because it would happen to find the register in the F4RC class first and return that. From the F4RC class, SDAG would extract f32 as the register type and then assert because of the invalid implied conversion between the f64 value and the f32 register. Instead, search all register classes. If a register class containing the the requested register has the requested type, then return that register class. Otherwise, as before, return the first register class found that contains the requested register. llvm-svn: 170436
* Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.Patrik Hagglund2012-12-131-1/+1
| | | | llvm-svn: 170148
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-111-30/+29
| | | | llvm-svn: 169854
* Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund2012-12-111-9/+10
| | | | | | from EVT. llvm-svn: 169849
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-111-4/+4
| | | | | | EVTs. llvm-svn: 169848
OpenPOWER on IntegriCloud