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| author | Chad Rosier <mcrosier@apple.com> | 2013-06-22 18:37:38 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2013-06-22 18:37:38 +0000 |
| commit | 295bd43adb9c514c53f6df861ae1c6e97c23a53a (patch) | |
| tree | d13c5eb42f4e12a882379551c8263b927fed7cbe /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 40d7f354b5637066a7ad3d50e19df482ee234d53 (diff) | |
| download | bcm5719-llvm-295bd43adb9c514c53f6df861ae1c6e97c23a53a.tar.gz bcm5719-llvm-295bd43adb9c514c53f6df861ae1c6e97c23a53a.zip | |
The getRegForInlineAsmConstraint function should only accept MVT value types.
llvm-svn: 184642
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index f02e3d6d2eb..69ddea4d8eb 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1992,7 +1992,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: getRegForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const { + MVT VT) const { if (Constraint[0] != '{') return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); |
