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path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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* Reapply "[CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors"Nikita Popov2019-01-151-4/+16
* Revert "[CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors"Nikita Popov2019-01-141-16/+4
* [CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectorsNikita Popov2019-01-141-4/+16
* [X86] Rename overly verbose method; NFCNikita Popov2019-01-131-2/+1
* Use getShiftAmountTy for shift amounts.Simon Pilgrim2019-01-121-1/+2
* [X86][AARCH64] Improve ISD::ABS supportSimon Pilgrim2019-01-121-0/+20
* Remove check for single use in ShrinkDemandedConstantStanislav Mekhanoshin2019-01-091-3/+0
* [TargetLowering][AMDGPU] Remove the SimplifyDemandedBits function that takes ...Craig Topper2019-01-071-50/+0
* Added single use check to ShrinkDemandedConstantStanislav Mekhanoshin2019-01-051-0/+3
* [SelectionDAG] Always use the version of computeKnownBits that returns a valu...Simon Pilgrim2018-12-211-5/+4
* [TargetLowering] Fix propagation of undefs in zero extension ops (PR40091)Simon Pilgrim2018-12-191-0/+14
* [TargetLowering] Fallback from SimplifyDemandedVectorElts to SimplifyDemanded...Simon Pilgrim2018-12-181-1/+8
* NFC: remove unused variableJF Bastien2018-12-171-1/+0
* [TargetLowering] Add DemandedElts mask to SimplifyDemandedBits (PR40000)Simon Pilgrim2018-12-171-42/+120
* [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-151-0/+2
* [TargetLowering] Add ISD::ROTL/ROTR vector expansionSimon Pilgrim2018-12-131-0/+45
* [TargetLowering] Add ISD::AND handling to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-121-0/+16
* [Intrinsic] Signed Fixed Point Multiplication IntrinsicLeonard Chan2018-12-121-5/+70
* [TargetLowering] Add ISD::EXTRACT_VECTOR_ELT support to SimplifyDemandedBitsSimon Pilgrim2018-12-111-0/+19
* [TargetLowering] Add UNDEF folding to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-101-1/+6
* [TargetLowering] Remove ISD::ANY_EXTEND/ANY_EXTEND_VECTOR_INREG opcodes from ...Simon Pilgrim2018-12-051-2/+0
* [SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467)Simon Pilgrim2018-12-051-0/+48
* [TargetLowering] SimplifyDemandedVectorElts - don't alter DemandedElts maskSimon Pilgrim2018-12-051-2/+3
* [SelectionDAG] Redefine isGAPlusOffset in terms of unwrapAddress. NFCI.Nirav Dave2018-12-041-1/+4
* [TargetLowering] expandFP_TO_UINT - avoid FPE due to out of range conversion ...Simon Pilgrim2018-12-041-11/+30
* [TargetLowering] Add SimplifyDemandedVectorElts support to EXTEND opcodesSimon Pilgrim2018-12-041-0/+17
* [SelectionDAG] Improve SimplifyDemandedBits to SimplifyDemandedVectorElts sim...Simon Pilgrim2018-12-011-5/+3
* [TargetLowering] SimplifyDemandedBits - only reduce known bits for integer co...Simon Pilgrim2018-11-211-1/+3
* [DAGCombine] Add calls to SimplifyDemandedVectorElts from visitINSERT_SUBVECT...Simon Pilgrim2018-11-201-1/+1
* [TargetLowering] Improve SimplifyDemandedVectorElts/SimplifyDemandedBits supportSimon Pilgrim2018-11-201-0/+17
* [TargetLowering] expandFP_TO_UINT - improve fp16 supportSimon Pilgrim2018-11-191-10/+18
* [TargetLowering] Cleanup more of the EXTEND demanded bits cases so that they ...Simon Pilgrim2018-11-161-10/+11
* [TargetLowering] Begin generalizing TargetLowering::expandFP_TO_SINT support....Simon Pilgrim2018-11-051-26/+26
* [LegalizeDAG] Add generic vector CTPOP expansion (PR32655)Simon Pilgrim2018-11-011-2/+13
* Check shouldReduceLoadWidth from SimplifySetCCStanislav Mekhanoshin2018-10-311-1/+2
* [Intrinsic] Signed and Unsigned Saturation Subtraction IntirnsicsLeonard Chan2018-10-291-16/+36
* [TargetLowering] Move i64/vXi64 to f32/vXf32 UINT_TO_FP handling to TargetLow...Simon Pilgrim2018-10-281-29/+72
* [VectorLegalizer] Enable TargetLowering::expandFP_TO_UINT support.Simon Pilgrim2018-10-281-0/+5
* [TargetLowering] Move LegalizeDAG FP_TO_UINT handling to TargetLowering::expa...Simon Pilgrim2018-10-271-0/+31
* [TargetLowering] Improve vXi64 UINT_TO_FP vXf64 support (P38226)Simon Pilgrim2018-10-251-0/+42
* [TargetLowering] Add SimplifyDemandedBitsForTargetNode callbackSimon Pilgrim2018-10-241-0/+24
* [LegalizeDAG] Share Vector/Scalar CTPOP ExpansionSimon Pilgrim2018-10-231-0/+49
* [LegalizeDAG] Share Vector/Scalar CTLZ ExpansionSimon Pilgrim2018-10-231-0/+53
* [LegalizeDAG] Share Vector/Scalar CTTZ ExpansionSimon Pilgrim2018-10-231-0/+55
* [Intrinsic] Unigned Saturation Addition IntrinsicLeonard Chan2018-10-221-22/+27
* DAG: Change behavior of fminnum/fmaxnum nodesMatt Arsenault2018-10-221-0/+29
* [Intrinsic] Signed Saturation Addition IntrinsicLeonard Chan2018-10-161-0/+43
* [SelectionDAG] allow FP binops in SimplifyDemandedVectorEltsSanjay Patel2018-10-151-1/+6
* [TargetLowering] SimplifyDemandedBits - rename demanded mask args. NFCI.Simon Pilgrim2018-10-101-80/+89
* [TargetLowering] SimplifyDemandedBits - pull out repeated getOperands. NFCI.Simon Pilgrim2018-10-101-119/+119
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