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authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-11-16 12:26:26 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-11-16 12:26:26 +0000
commit3c8baf4f902c7168b10ac465ba46973c2ef12fc1 (patch)
tree53a5acec447d6792589b6cd443e8d305bbaf93cb /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
parent22c9f7b296a48d5d3552d776a05f8cb1ff5d921c (diff)
downloadbcm5719-llvm-3c8baf4f902c7168b10ac465ba46973c2ef12fc1.tar.gz
bcm5719-llvm-3c8baf4f902c7168b10ac465ba46973c2ef12fc1.zip
[TargetLowering] Cleanup more of the EXTEND demanded bits cases so that they match. NFCI.
Use the same variable names etc. llvm-svn: 347045
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp21
1 files changed, 11 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 2bc9090428b..76e2be650b3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1084,19 +1084,19 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
break;
}
case ISD::ZERO_EXTEND: {
- unsigned OperandBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
+ SDValue Src = Op.getOperand(0);
+ unsigned InBits = Src.getScalarValueSizeInBits();
// If none of the top bits are demanded, convert this into an any_extend.
- if (DemandedBits.getActiveBits() <= OperandBitWidth)
- return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
- Op.getOperand(0)));
+ if (DemandedBits.getActiveBits() <= InBits)
+ return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, Src));
- APInt InMask = DemandedBits.trunc(OperandBitWidth);
- if (SimplifyDemandedBits(Op.getOperand(0), InMask, Known, TLO, Depth+1))
+ APInt InDemandedBits = DemandedBits.trunc(InBits);
+ if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth+1))
return true;
assert(!Known.hasConflict() && "Bits known to be one AND zero?");
Known = Known.zext(BitWidth);
- Known.Zero.setBitsFrom(OperandBitWidth);
+ Known.Zero.setBitsFrom(InBits);
break;
}
case ISD::SIGN_EXTEND: {
@@ -1143,9 +1143,10 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
break;
}
case ISD::ANY_EXTEND: {
- unsigned OperandBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
- APInt InMask = DemandedBits.trunc(OperandBitWidth);
- if (SimplifyDemandedBits(Op.getOperand(0), InMask, Known, TLO, Depth+1))
+ SDValue Src = Op.getOperand(0);
+ unsigned InBits = Src.getScalarValueSizeInBits();
+ APInt InDemandedBits = DemandedBits.trunc(InBits);
+ if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth+1))
return true;
assert(!Known.hasConflict() && "Bits known to be one AND zero?");
Known = Known.zext(BitWidth);
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