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* Teach TargetData to handle 'preferred' alignment for each target, and useChris Lattner2007-01-201-11/+4
| | | | | | these alignment amounts to align scalars when we can. Patch by Scott Michel! llvm-svn: 33409
* For PR1043:Zhou Sheng2007-01-111-12/+12
| | | | | | | Merge ConstantIntegral and ConstantBool into ConstantInt. Remove ConstantIntegral and ConstantBool from LLVM. llvm-svn: 33073
* remove support for llvm.isunorderedChris Lattner2007-01-071-22/+0
| | | | llvm-svn: 32992
* GEP subscript is interpreted as a signed value.Evan Cheng2007-01-051-1/+1
| | | | llvm-svn: 32888
* fix PowerPC/2007-01-04-ArgExtension.ll, a bug handling K&R prototypes withChris Lattner2007-01-041-4/+6
| | | | | | the recent signless changes. llvm-svn: 32884
* Legalizer doesn't do an ANY_EXTEND if we don't ask for one so make sureReid Spencer2007-01-031-1/+1
| | | | | | | that we default to an ANY_EXTEND if no parameter attribute is set on the result value of a function. llvm-svn: 32836
* Restore previous behavior of defaulting to ZEXT. This works around twoReid Spencer2007-01-031-7/+2
| | | | | | | | things: (1) preventing PR1071 and (2) working around missing parameter attributes for bool type. (2) will be fixed shortly. When PR1071 is fixed, this patch should be undone. llvm-svn: 32831
* Two changes:Reid Spencer2007-01-031-5/+12
| | | | | | | | | | | 1. Switch expression and cases are compared signed and are sign extended. 2. For function results needing extended, do SIGN_EXTEND if the SExtAttribute is set and ZERO_EXTEND if the ZExtAttribute is set, otherwise just let the Legalizer do ANY_EXTEND. This fixes the recent regression in kimwitu++ and probably the llvm-gcc bootstrap issue we had today. llvm-svn: 32830
* For PR950:Reid Spencer2006-12-311-53/+55
| | | | | | | | | | | | | | | | | | Three changes: 1. Convert signed integer types to signless versions. 2. Implement the @sext and @zext parameter attributes. Previously the type of an function parameter was used to determine whether it should be sign extended or zero extended before the call. This information is now communicated via the function type's parameter attributes. 3. The interface to LowerCallTo had to be changed in order to accommodate the parameter attribute information. Although it would have been convenient to pass in the FunctionType itself, there isn't always one present in the caller. Consequently, a signedness indication for the result type and for each parameter was provided for in the interface to this method. All implementations were changed to make the adjustment necessary. llvm-svn: 32788
* For PR950:Reid Spencer2006-12-231-104/+89
| | | | | | | | This patch removes the SetCC instructions and replaces them with the ICmp and FCmp instructions. The SetCondInst instruction has been removed and been replaced with ICmpInst and FCmpInst. llvm-svn: 32751
* getLoad() and getStore() calls missed SVOffset operand. Thanks to Dan GohmanEvan Cheng2006-12-201-2/+2
| | | | | | for pointing it out! llvm-svn: 32712
* Fix PR1049 and CodeGen/Generic/2006-12-16-InlineAsmCrash.llChris Lattner2006-12-161-1/+2
| | | | | | | by producing target constants instead of constants. Constants can get selected to li/movri instructions, which causes the scheduler to explode. llvm-svn: 32633
* More soft-fp work.Evan Cheng2006-12-131-33/+32
| | | | llvm-svn: 32559
* Replace CastInst::createInferredCast calls with more accurate castReid Spencer2006-12-131-5/+5
| | | | | | creation calls. llvm-svn: 32521
* Expand i32/i64 CopyToReg f32/f64 to BIT_CONVERT + CopyToReg.Evan Cheng2006-12-121-0/+3
| | | | llvm-svn: 32493
* Expand formal arguments and call arguments recursively: e.g. f64 -> i64 -> 2 ↵Evan Cheng2006-12-121-45/+76
| | | | | | x i32. llvm-svn: 32476
* Cleaned setjmp/longjmp lowering interfaces. Now we're producing rightAnton Korobeynikov2006-12-101-2/+2
| | | | | | | code (both asm & cbe) for Mingw32 target. Removed autoconf checks for underscored versions of setjmp/longjmp. llvm-svn: 32415
* Preliminary soft float support.Evan Cheng2006-12-091-3/+12
| | | | llvm-svn: 32394
* Removing even more <iostream> includes.Bill Wendling2006-12-071-13/+12
| | | | llvm-svn: 32320
* Fix for PR1023 by Dan Gohman.Evan Cheng2006-11-291-1/+1
| | | | llvm-svn: 32003
* Fix for PR1022 (folding loads of static initializers) by Dan Gohman.Evan Cheng2006-11-291-1/+1
| | | | llvm-svn: 32000
* add a hook to allow targets to hack on inline asms to lower them to llvmChris Lattner2006-11-291-1/+13
| | | | | | when they want to. llvm-svn: 31997
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-1/+2
| | | | | | of opcode and number of operands. llvm-svn: 31947
* For PR950:Reid Spencer2006-11-271-56/+140
| | | | | | | | | | The long awaited CAST patch. This introduces 12 new instructions into LLVM to replace the cast instruction. Corresponding changes throughout LLVM are provided. This passes llvm-test, llvm/test, and SPEC CPUINT2000 with the exception of 175.vpr which fails only on a slight floating point output difference. llvm-svn: 31931
* For PR950:Reid Spencer2006-11-201-0/+56
| | | | | | | | First in a series of patches to convert SetCondInst into ICmpInst and FCmpInst using only two opcodes and having the instructions contain their predicate value. Nothing uses these classes yet. More patches to follow. llvm-svn: 31867
* remove dead #includeChris Lattner2006-11-151-1/+0
| | | | llvm-svn: 31753
* commentateChris Lattner2006-11-101-0/+2
| | | | llvm-svn: 31627
* For PR950:Reid Spencer2006-11-081-4/+2
| | | | | | | | This patch converts the old SHR instruction into two instructions, AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not dependent on the sign of their operands. llvm-svn: 31542
* For PR786:Reid Spencer2006-11-021-6/+0
| | | | | | | | | | Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting fall out by removing unused variables. Remaining warnings have to do with unused functions (I didn't want to delete code without review) and unused variables in generated code. Maintainers should clean up the remaining issues when they see them. All changes pass DejaGnu tests and Olden. llvm-svn: 31380
* For PR950:Reid Spencer2006-11-021-8/+4
| | | | | | Replace the REM instruction with UREM, SREM and FREM. llvm-svn: 31369
* Allow the getRegForInlineAsmConstraint method to return a register class withChris Lattner2006-11-021-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | no fixes physreg. Treat this as permission to use any register in the register class. When this happens and it is safe, allow the llvm register allcoator to allocate the register instead of doing it at isel time. This eliminates a ton of copies around common inline asms. For example: int test2(int Y, int X) { asm("foo %0, %1" : "=r"(X): "r"(X)); return X; } now compiles to: _test2: foo r3, r4 blr instead of: _test2: mr r2, r4 foo r2, r2 mr r3, r2 blr GCC produces: _test2: foo r4, r4 mr r3,r4 blr llvm-svn: 31366
* Compile CodeGen/PowerPC/fp-branch.ll to:Chris Lattner2006-10-311-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | _intcoord_cond_next55: LBB1_3: ;cond_next55 lis r2, ha16(LCPI1_0) lfs f0, lo16(LCPI1_0)(r2) fcmpu cr0, f1, f0 blt cr0, LBB1_2 ;cond_next62.exitStub LBB1_1: ;bb72.exitStub li r3, 1 blr LBB1_2: ;cond_next62.exitStub li r3, 0 blr instead of: _intcoord_cond_next55: LBB1_3: ;cond_next55 lis r2, ha16(LCPI1_0) lfs f0, lo16(LCPI1_0)(r2) fcmpu cr0, f1, f0 bge cr0, LBB1_1 ;bb72.exitStub LBB1_4: ;cond_next55 lis r2, ha16(LCPI1_0) lfs f0, lo16(LCPI1_0)(r2) fcmpu cr0, f1, f0 bnu cr0, LBB1_2 ;cond_next62.exitStub LBB1_1: ;bb72.exitStub li r3, 1 blr LBB1_2: ;cond_next62.exitStub li r3, 0 blr llvm-svn: 31330
* look through isunordered to inline it into branch blocks.Chris Lattner2006-10-311-12/+43
| | | | llvm-svn: 31328
* TargetLowering::isOperandValidForConstraintChris Lattner2006-10-311-2/+7
| | | | llvm-svn: 31319
* Turn an assert into an error message. This is commonly triggered whenChris Lattner2006-10-311-1/+5
| | | | | | | we don't support a specific constraint yet. When this happens, print the unsupported constraint. llvm-svn: 31310
* Lower jumptable to BR_JT. The legalizer can lower it to a BRIND or let the ↵Evan Cheng2006-10-301-28/+7
| | | | | | target custom lower it. llvm-svn: 31293
* fix Generic/2006-10-29-Crash.llChris Lattner2006-10-291-1/+9
| | | | llvm-svn: 31281
* Fix a load folding issue that Evan noticed: there is no need to export valuesChris Lattner2006-10-291-7/+17
| | | | | | used by comparisons in the main block. llvm-svn: 31279
* split critical edges more carefully and intelligently. In particular, criticalChris Lattner2006-10-281-4/+61
| | | | | | | | edges whose destinations are not phi nodes don't bother us. Also, share split edges, since the split edge can't have a phi. This significantly reduces the complexity of generated code in some cases. llvm-svn: 31274
* Split *all* critical edges before isel. This resolves issues with spill codeChris Lattner2006-10-281-44/+8
| | | | | | | | | being inserted on unsplit critical edges, which introduces (sometimes large amounts of) partially dead spill code. This also fixes PR925 + CodeGen/Generic/switch-crit-edge-constant.ll llvm-svn: 31260
* Fix a bug in merged condition handling ↵Chris Lattner2006-10-271-67/+110
| | | | | | | | | | (CodeGen/Generic/2006-10-27-CondFolding.ll). Add many fewer CFG edges and PHI node entries. If there is a switch which has the same block as multiple destinations, only add that block once as a successor/phi node (in the jumptable case) llvm-svn: 31242
* remove debug codeChris Lattner2006-10-271-2/+0
| | | | llvm-svn: 31233
* Codegen cond&cond with two branches. This compiles (f.e.) ↵Chris Lattner2006-10-271-15/+35
| | | | | | | | | | | | | | | | | | | | | | | | PowerPC/and-branch.ll to: cmpwi cr0, r4, 4 bgt cr0, LBB1_2 ;UnifiedReturnBlock LBB1_3: ;entry cmplwi cr0, r3, 0 bne cr0, LBB1_2 ;UnifiedReturnBlock instead of: cmpwi cr7, r4, 4 mfcr r2 addic r4, r3, -1 subfe r3, r4, r3 rlwinm r2, r2, 30, 31, 31 or r2, r2, r3 cmplwi cr0, r2, 0 bne cr0, LBB1_2 ;UnifiedReturnBlock LBB1_1: ;cond_true llvm-svn: 31232
* Turn conditions like x<Y|z==q into multiple blocks.Chris Lattner2006-10-271-19/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This compiles Regression/CodeGen/X86/or-branch.ll into: _foo: subl $12, %esp call L_bar$stub movl 20(%esp), %eax movl 16(%esp), %ecx cmpl $5, %eax jl LBB1_1 #cond_true LBB1_3: #entry testl %ecx, %ecx jne LBB1_2 #UnifiedReturnBlock LBB1_1: #cond_true call L_bar$stub addl $12, %esp ret LBB1_2: #UnifiedReturnBlock addl $12, %esp ret instead of: _foo: subl $12, %esp call L_bar$stub movl 20(%esp), %eax movl 16(%esp), %ecx cmpl $4, %eax setg %al testl %ecx, %ecx setne %cl testb %cl, %al jne LBB1_2 #UnifiedReturnBlock LBB1_1: #cond_true call L_bar$stub addl $12, %esp ret LBB1_2: #UnifiedReturnBlock addl $12, %esp ret And on ppc to: cmpwi cr0, r29, 5 blt cr0, LBB1_1 ;cond_true LBB1_3: ;entry cmplwi cr0, r30, 0 bne cr0, LBB1_2 ;UnifiedReturnBlock instead of: cmpwi cr7, r4, 4 mfcr r2 addic r4, r3, -1 subfe r30, r4, r3 rlwinm r29, r2, 30, 31, 31 and r2, r29, r30 cmplwi cr0, r2, 0 bne cr0, LBB1_2 ;UnifiedReturnBlock llvm-svn: 31230
* For PR950:Reid Spencer2006-10-261-24/+44
| | | | | | | | Make necessary changes to support DIV -> [SUF]Div. This changes llvm to have three division instructions: signed, unsigned, floating point. The bytecode and assembler are bacwards compatible, however. llvm-svn: 31195
* visitSwitchCase knows how to insert conditional branches well. ChangeChris Lattner2006-10-241-37/+8
| | | | | | visitBr to just call visitSwitchCase, eliminating duplicate logic. llvm-svn: 31167
* Generalize CaseBlock a bit more:Chris Lattner2006-10-241-57/+74
| | | | | | | Rename LHSBB/RHSBB to TrueBB/FalseBB. Allow the RHS value to be null, in which case the LHS is treated as a bool. llvm-svn: 31166
* generalize 'CaseBlock'. It really allows any comparison to be inserted.Chris Lattner2006-10-241-3/+2
| | | | llvm-svn: 31161
* Minor tweak. Instead of generating:Chris Lattner2006-10-231-0/+13
| | | | | | | | | | | | | | | | | | | | | | | movl 32(%esp), %eax cmpl $1, %eax je LBB1_1 #bb LBB1_4: #entry cmpl $2, %eax je LBB1_2 #bb2 jmp LBB1_3 #UnifiedReturnBlock LBB1_1: #bb notice that we would miss the fall through and emit this instead: movl 32(%esp), %eax cmpl $2, %eax je LBB1_2 #bb2 LBB1_4: #entry cmpl $1, %eax jne LBB1_3 #UnifiedReturnBlock LBB1_1: #bb llvm-svn: 31130
* Fix phi node updating for switches lowered to linear sequences of branches.Chris Lattner2006-10-221-1/+13
| | | | llvm-svn: 31125
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