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authorReid Spencer <rspencer@reidspencer.com>2006-11-08 06:47:33 +0000
committerReid Spencer <rspencer@reidspencer.com>2006-11-08 06:47:33 +0000
commitfdff938a7e4988da80be038acb1c6717d61b531a (patch)
tree2270b132b8a1fe22f63b56653ebf71dac480ad84 /llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
parent41f6c7cfb24169288c69d0dc5abf5518c142b76e (diff)
downloadbcm5719-llvm-fdff938a7e4988da80be038acb1c6717d61b531a.tar.gz
bcm5719-llvm-fdff938a7e4988da80be038acb1c6717d61b531a.zip
For PR950:
This patch converts the old SHR instruction into two instructions, AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not dependent on the sign of their operands. llvm-svn: 31542
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp6
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index d00b9966ede..26f3bffe84b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -538,10 +538,8 @@ public:
void visitOr (User &I) { visitIntBinary(I, ISD::OR, ISD::VOR); }
void visitXor(User &I) { visitIntBinary(I, ISD::XOR, ISD::VXOR); }
void visitShl(User &I) { visitShift(I, ISD::SHL); }
- void visitShr(User &I) {
- visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
- }
-
+ void visitLShr(User &I) { visitShift(I, ISD::SRL); }
+ void visitAShr(User &I) { visitShift(I, ISD::SRA); }
void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
ISD::CondCode FPOpc);
void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
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