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* Added temp flag -misched-bench for staging in default changes.Andrew Trick2013-09-261-1/+1
| | | | llvm-svn: 191423
* whitespaceAndrew Trick2013-09-261-2/+2
| | | | llvm-svn: 191422
* [stackprotector] Allow for copies from vreg -> vreg to be in a terminator ↵Michael Gottesman2013-09-241-6/+26
| | | | | | | | | | | sequence. Sometimes a copy from a vreg -> vreg sneaks into the middle of a terminator sequence. It is safe to slice this into the stack protector success bb. This fixes PR16979. llvm-svn: 191260
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-5/+5
| | | | | | | | | | | | | | | | | Previously, the DAGISel function WalkChainUsers was spotting that it had entered already-selected territory by whether a node was a MachineNode (amongst other things). Since it's fairly common practice to insert MachineNodes during ISelLowering, this was not the correct check. Looking around, it seems that other nodes get their NodeId set to -1 upon selection, so this makes sure the same thing happens to all MachineNodes and uses that characteristic to determine whether we should stop looking for a loop during selection. This should fix PR15840. llvm-svn: 191165
* Debug info: Fix PR16736 and rdar://problem/14990587.Adrian Prantl2013-09-161-1/+1
| | | | | | | A DBG_VALUE is register-indirect iff the first operand is a register _and_ the second operand is an immediate. llvm-svn: 190821
* [stackprotector] When finding the split point to splice off the end of a ↵Michael Gottesman2013-08-221-9/+44
| | | | | | | | parentmbb into a successmbb, include any DBG_VALUE MI. Fix for PR16954. llvm-svn: 188987
* Remove unused variables that crept in.Michael Gottesman2013-08-201-6/+0
| | | | llvm-svn: 188761
* Teach selectiondag how to handle the stackprotectorcheck intrinsic.Michael Gottesman2013-08-201-4/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, generation of stack protectors was done exclusively in the pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated splitting basic blocks at the IR level to create the success/failure basic blocks in the tail of the basic block in question. As a result of this, calls that would have qualified for the sibling call optimization were no longer eligible for optimization since said calls were no longer right in the "tail position" (i.e. the immediate predecessor of a ReturnInst instruction). Then it was noticed that since the sibling call optimization causes the callee to reuse the caller's stack, if we could delay the generation of the stack protector check until later in CodeGen after the sibling call decision was made, we get both the tail call optimization and the stack protector check! A few goals in solving this problem were: 1. Preserve the architecture independence of stack protector generation. 2. Preserve the normal IR level stack protector check for platforms like OpenBSD for which we support platform specific stack protector generation. The main problem that guided the present solution is that one can not solve this problem in an architecture independent manner at the IR level only. This is because: 1. The decision on whether or not to perform a sibling call on certain platforms (for instance i386) requires lower level information related to available registers that can not be known at the IR level. 2. Even if the previous point were not true, the decision on whether to perform a tail call is done in LowerCallTo in SelectionDAG which occurs after the Stack Protector Pass. As a result, one would need to put the relevant callinst into the stack protector check success basic block (where the return inst is placed) and then move it back later at SelectionDAG/MI time before the stack protector check if the tail call optimization failed. The MI level option was nixed immediately since it would require platform specific pattern matching. The SelectionDAG level option was nixed because SelectionDAG only processes one IR level basic block at a time implying one could not create a DAG Combine to move the callinst. To get around this problem a few things were realized: 1. While one can not handle multiple IR level basic blocks at the SelectionDAG Level, one can generate multiple machine basic blocks for one IR level basic block. This is how we handle bit tests and switches. 2. At the MI level, tail calls are represented via a special return MIInst called "tcreturn". Thus if we know the basic block in which we wish to insert the stack protector check, we get the correct behavior by always inserting the stack protector check right before the return statement. This is a "magical transformation" since no matter where the stack protector check intrinsic is, we always insert the stack protector check code at the end of the BB. Given the aforementioned constraints, the following solution was devised: 1. On platforms that do not support SelectionDAG stack protector check generation, allow for the normal IR level stack protector check generation to continue. 2. On platforms that do support SelectionDAG stack protector check generation: a. Use the IR level stack protector pass to decide if a stack protector is required/which BB we insert the stack protector check in by reusing the logic already therein. If we wish to generate a stack protector check in a basic block, we place a special IR intrinsic called llvm.stackprotectorcheck right before the BB's returninst or if there is a callinst that could potentially be sibling call optimized, before the call inst. b. Then when a BB with said intrinsic is processed, we codegen the BB normally via SelectBasicBlock. In said process, when we visit the stack protector check, we do not actually emit anything into the BB. Instead, we just initialize the stack protector descriptor class (which involves stashing information/creating the success mbbb and the failure mbb if we have not created one for this function yet) and export the guard variable that we are going to compare. c. After we finish selecting the basic block, in FinishBasicBlock if the StackProtectorDescriptor attached to the SelectionDAGBuilder is initialized, we first find a splice point in the parent basic block before the terminator and then splice the terminator of said basic block into the success basic block. Then we code-gen a new tail for the parent basic block consisting of the two loads, the comparison, and finally two branches to the success/failure basic blocks. We conclude by code-gening the failure basic block if we have not code-gened it already (all stack protector checks we generate in the same function, use the same failure basic block). llvm-svn: 188755
* ARM: Fix more fast-isel verifier failures.Jim Grosbach2013-08-161-0/+4
| | | | | | | | | | | | | Teach the generic instruction selection helper functions to constrain the register classes of their input operands. For non-physical register references, the generic code needs to be careful not to mess that up when replacing references to result registers. As the comment indicates for MachineRegisterInfo::replaceRegWith(), it's important to call constrainRegClass() first. rdar://12594152 llvm-svn: 188593
* Replace getValueType().getSimpleVT() with getSimpleValueType().Craig Topper2013-08-151-1/+1
| | | | llvm-svn: 188442
* Reimplement isPotentiallyReachable to make nocapture deduction much stronger.Nick Lewycky2013-07-271-0/+1
| | | | | | | | | | Adds unit tests for it too. Split BasicBlockUtils into an analysis-half and a transforms-half, and put the analysis bits into a new Analysis/CFG.{h,cpp}. Promote isPotentiallyReachable into llvm::isPotentiallyReachable and move it into Analysis/CFG. llvm-svn: 187283
* Reapply an improved version of r180816/180817.Adrian Prantl2013-07-091-7/+9
| | | | | | | | | | | | | | | Change the informal convention of DBG_VALUE machine instructions so that we can express a register-indirect address with an offset of 0. The old convention was that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain register values the combination reg, reg is used. MachineInstrBuilder::BuildMI knows how to build the new DBG_VALUES. rdar://problem/13658587 llvm-svn: 185966
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-041-4/+7
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. llvm-svn: 185617
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-7/+4
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." llvm-svn: 185600
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-031-4/+7
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. llvm-svn: 185595
* Use SmallVectorImpl::const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-031-4/+4
| | | | | | specifying the vector size. llvm-svn: 185514
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-11/+14
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* Debug Info: Simplify Frame Index handling in DBG_VALUE Machine InstructionsDavid Blaikie2013-06-161-1/+4
| | | | | | | | | | | | | | | | | | | | Rather than using the full power of target-specific addressing modes in DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This reduces the complexity of debug info handling down to two representations of values (reg+offset and frame index+offset) rather than three or four. Ideally we could ensure that frame indicies had been eliminated by the time we reached an assembly or dwarf generation, but I haven't spent the time to figure out where the FIs are leaking through into that & whether there's a good place to convert them. Some FI+offset=>reg+offset conversion is done (see PrologEpilogInserter, for example) which is necessary for some SelectionDAG assumptions about registers, I believe, but it might be possible to make this a more thorough conversion & ensure there are no remaining FIs no matter how instruction selection is performed. llvm-svn: 184066
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-18/+17
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* Don't cache the TargetLoweringInfo object inside of the FunctionLowering object.Bill Wendling2013-06-061-1/+1
| | | | | | | | The TargetLoweringInfo object is owned by the TargetMachine. In the future, the TargetMachine object may change, which may also change the TargetLoweringInfo object. llvm-svn: 183356
* Track IR ordering of SelectionDAG nodes 3/4.Andrew Trick2013-05-251-3/+1
| | | | | | | Remove the old IR ordering mechanism and switch to new one. Fix unit test failures. llvm-svn: 182704
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-4/+4
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Temporarily revert "Change the informal convention of DBG_VALUE so that we ↵Adrian Prantl2013-04-301-10/+7
| | | | | | | | | | can express a" because it breaks some buildbots. This reverts commit 180816. llvm-svn: 180819
* Change the informal convention of DBG_VALUE so that we can express aAdrian Prantl2013-04-301-7/+10
| | | | | | | | | | | | register-indirect address with an offset of 0. It used to be that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain registers use the combination reg, reg. rdar://problem/13658587 llvm-svn: 180816
* Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'mEli Bendersky2013-04-191-79/+1
| | | | | | | trying to move as much FastISel logic as possible out of the main path in SelectionDAGISel - intermixing them just adds confusion. llvm-svn: 179902
* ArrayRefize getMachineNode(). No functionality change.Michael Liao2013-04-191-1/+1
| | | | llvm-svn: 179901
* Use dbgs() consistently for -debug printoutsEli Bendersky2013-04-191-13/+13
| | | | llvm-svn: 179894
* Add some more stats for fast isel vs. SelectionDAG, w.r.t lowering functionEli Bendersky2013-04-191-1/+10
| | | | | | arguments in entry BBs. llvm-svn: 179824
* Move SDNode order propagation to SDNodeOrdering, which also fixes a missedJustin Holewinski2013-03-201-0/+2
| | | | | | | | case of order propagation during isel. Thanks Owen for the suggestion! llvm-svn: 177525
* Propagate DAG node ordering during type legalization and instruction selectionJustin Holewinski2013-03-201-1/+3
| | | | | | | | A node's ordering is only propagated during legalization if (a) the new node does not have an ordering (is not a CSE'd node), or (b) the new node has an ordering that is higher than the node being legalized. llvm-svn: 177465
* Reset some of the target options which affect code generation.Bill Wendling2013-03-131-0/+1
| | | | | | | | This doesn't reset all of the target options within the TargetOptions object. This is because some of those are ABI-specific and must be determined if it's okay to change those on the fly. llvm-svn: 176986
* Disable statistics on Release builds and move tests that depend on -stats.Jan Wen Voung2013-03-081-13/+11
| | | | | | | | | | | | | | | | | Summary: Statistics are still available in Release+Asserts (any +Asserts builds), and stats can also be turned on with LLVM_ENABLE_STATS. Move some of the FastISel stats that were moved under DEBUG() back out of DEBUG(), since stats are disabled across the board now. Many tests depend on grepping "-stats" output. Move those into a orig_dir/Stats/. so that they can be marked as unsupported when building without statistics. Differential Revision: http://llvm-reviews.chandlerc.com/D486 llvm-svn: 176733
* ArrayRefize some code. No functionality change.Benjamin Kramer2013-03-071-3/+1
| | | | llvm-svn: 176648
* No need to go through int64 and APInt when generating a new constant.Nadav Rotem2013-03-071-3/+3
| | | | llvm-svn: 176615
* Remove duplicate line and move another closer to its actual useEli Bendersky2013-03-011-3/+1
| | | | llvm-svn: 176391
* A small refactoring + adding comments.Eli Bendersky2013-02-281-7/+4
| | | | | | | | | | | SelectionDAGIsel::LowerArguments needs a function, not a basic block. So it makes sense to pass it the function instead of extracting a basic-block from the function and then tossing it. This is also more self-documenting (functions have arguments, BBs don't). In addition, added comments to a couple of Select* methods. llvm-svn: 176305
* Remove unnecessary cast to void.Eric Christopher2013-02-271-1/+0
| | | | llvm-svn: 176222
* Silence the unused variable warning. Nadav Rotem2013-02-271-5/+7
| | | | llvm-svn: 176218
* The FastISEL should be fast. But when we record statistics we use atomic ↵Nadav Rotem2013-02-271-9/+10
| | | | | | | | operations to increment the counters. This patch disables the counters on non-debug builds. This reduces the runtime of SelectionDAGISel::SelectCodeCommon by ~5%. llvm-svn: 176214
* Fix wording.Chad Rosier2013-02-251-3/+4
| | | | llvm-svn: 176055
* [fast-isel] Add X86FastIsel::FastLowerArguments to handle functions with 6 orChad Rosier2013-02-251-0/+10
| | | | | | | | | | fewer scalar integer (i32 or i64) arguments. It completely eliminates the need for SDISel for trivial functions. Also, add the new llc -fast-isel-abort-args option, which is similar to -fast-isel-abort option, but for formal argument lowering. llvm-svn: 176052
* [ms-inline asm] Remove a redundant call to the setHasMSInlineAsm function.Chad Rosier2013-02-181-2/+1
| | | | llvm-svn: 175456
* [ms-inline asm] Fix undefined behavior to reset hasMSInlineAsm in advance of ↵NAKAMURA Takumi2013-02-181-0/+1
| | | | | | SelectAllBasicBlocks(). llvm-svn: 175422
* [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.Chad Rosier2013-02-161-14/+17
| | | | | | | | | | | If the frame pointer is omitted, and any stack changes occur in the inline assembly, e.g.: "pusha", then any C local variable or C argument references will be incorrect. I pass no judgement on anyone who would do such a thing. ;) rdar://13218191 llvm-svn: 175334
* Use the 'target-features' and 'target-cpu' attributes to reset the subtarget ↵Bill Wendling2013-02-151-0/+4
| | | | | | | | | | features. If two functions require different features (e.g., `-mno-sse' vs. `-msse') then we want to honor that, especially during LTO. We can do that by resetting the subtarget's features depending upon the 'target-feature' attribute. llvm-svn: 175314
* Currently, codegen may spent some time in SDISel passes even if an entireEvan Cheng2013-02-111-7/+13
| | | | | | | | | | | | | | function is successfully handled by fast-isel. That's because function arguments are *always* handled by SDISel. Introduce FastLowerArguments to allow each target to provide hook to handle formal argument lowering. As a proof-of-concept, add ARMFastIsel::FastLowerArguments to handle functions with 4 or fewer scalar integer (i8, i16, or i32) arguments. It completely eliminates the need for SDISel for trivial functions. rdar://13163905 llvm-svn: 174855
* Move TargetTransformInfo to live under the Analysis library. This noChandler Carruth2013-01-071-1/+1
| | | | | | | longer would violate any dependency layering and it is in fact an analysis. =] llvm-svn: 171686
* Funnel the actual TargetTransformInfo pass from the SelectionDAGISelChandler Carruth2013-01-051-1/+3
| | | | | | | | | pass into the SelectionDAG itself rather than snooping on the implementation of that pass as exposed by the TargetMachine. This removes the last direct client of the ScalarTargetTransformInfo class outside of the TTI pass implementation. llvm-svn: 171625
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-8/+8
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Use MachineInstrBuilder for PHI nodes in SelectionDAGISel.Jakob Stoklund Olesen2012-12-201-50/+25
| | | | llvm-svn: 170716
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