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path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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* Inline implVisitAluOverflow by introducing a nested switch to convert the ↵Craig Topper2012-04-111-18/+18
| | | | | | intrinsic to an nodetype. llvm-svn: 154478
* Optimize code a bit by calling push_back only once in some loops. Reduces ↵Craig Topper2012-04-111-26/+24
| | | | | | compiled code size a bit. llvm-svn: 154473
* Optimize code a bit. No functional change intended.Craig Topper2012-04-081-9/+9
| | | | llvm-svn: 154299
* Simplify code that tries to do vector extracts for shuffles when the mask ↵Craig Topper2012-04-081-12/+8
| | | | | | width and the input vector widths don't match. No need to check the min and max are in range before calculating the start index. The range check after having the start index is sufficient. Also no need to check for an extract from the beginning differently. llvm-svn: 154295
* Turn avx2 vinserti128 intrinsic calls into INSERT_SUBVECTOR DAG nodes and ↵Craig Topper2012-04-071-1/+2
| | | | | | remove patterns for selecting the intrinsic. Similar was already done for avx1. llvm-svn: 154272
* Remove 'else' after 'if' that ends in return.Craig Topper2012-04-071-1/+1
| | | | llvm-svn: 154267
* Teach CodeGen's version of computeMaskedBits to understand the range metadata.Rafael Espindola2012-03-311-1/+3
| | | | | | | | This is the CodeGen equivalent of r153747. I tested that there is not noticeable performance difference with any combination of -O0/-O2 /-g when compiling gcc as a single compilation unit. llvm-svn: 153817
* More debug output.Eric Christopher2012-03-281-1/+2
| | | | llvm-svn: 153571
* Add a debug statement.Eric Christopher2012-03-261-1/+3
| | | | llvm-svn: 153428
* Assign node orders to target intrinsics which do not produce results. ↵Evan Cheng2012-03-221-0/+6
| | | | | | rdar://11096639 llvm-svn: 153269
* Add another debug statement.Eric Christopher2012-03-151-1/+3
| | | | llvm-svn: 152843
* llvm::SwitchInstStepan Dyatkovskiy2012-03-111-1/+1
| | | | | | | Renamed methods caseBegin, caseEnd and caseDefault with case_begin, case_end, and case_default. Added some notes relative to case iterators. llvm-svn: 152532
* Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:Stepan Dyatkovskiy2012-03-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*". ConstCaseIt is just a read-only iterator. CaseIt is read-write iterator; it allows to change case successor and case value. Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters. Main way of iterator usage looks like this: SwitchInst *SI = ... // intialize it somehow for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) { BasicBlock *BB = i.getCaseSuccessor(); ConstantInt *V = i.getCaseValue(); // Do something. } If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method. If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method. There are also related changes in llvm-clients: klee and clang. llvm-svn: 152297
* Fix warnings about adding a bool to a string.Bill Wendling2012-03-051-2/+2
| | | | | | Patch by Sean Silva! llvm-svn: 152042
* Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even ↵James Molloy2012-03-011-2/+4
| | | | | | | | though they could have sideeffects. Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone". llvm-svn: 151807
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-281-3/+5
| | | | | | direct call. llvm-svn: 151645
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-281-5/+3
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Code cleanup following CR by Duncan.Nadav Rotem2012-02-281-5/+3
| | | | llvm-svn: 151627
* Fix a bug in the code that builds SDNodes from vector GEPs.Nadav Rotem2012-02-281-0/+4
| | | | | | | | | | | When the GEP index is a vector of pointers, the code that calculated the size of the element started from the vector type, and not the contained pointer type. As a result, instead of looking at the data element pointed by the vector, this code used the size of the vector. This works for 32bit members (on 32bit systems), but not for other types. Added code to peel the vector type and added a test. llvm-svn: 151626
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-3/+5
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* SDAGBuilder: Remove register sets that were never read and prune dead code ↵Benjamin Kramer2012-02-241-63/+3
| | | | | | surrounding it. llvm-svn: 151364
* Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove ↵Pete Cooper2012-02-241-0/+15
| | | | | | duplicate patterns for selecting the intrinsics llvm-svn: 151342
* If the Address of a variable is an argument then treat the entireEric Christopher2012-02-241-3/+7
| | | | | | | | | | | variable declaration as an argument because we want that address anyhow for our debug information. This seems to fix rdar://9965111, at least we have more debug information than before and from reading the assembly it appears to be the correct location. llvm-svn: 151335
* Allow an integer to be converted into an MMX type when it's used in an inlineBill Wendling2012-02-231-2/+8
| | | | | | | asm. <rdar://problem/10106006> llvm-svn: 151303
* More newline cleanups.Eric Christopher2012-02-231-3/+3
| | | | llvm-svn: 151235
* Add some handy-dandy newlines.Eric Christopher2012-02-231-2/+2
| | | | llvm-svn: 151234
* Properly emit _fltused with FastISel. Refactor to share code with SDAG.Michael J. Spencer2012-02-221-16/+1
| | | | | | Patch by Joe Groff! llvm-svn: 151183
* Rename getExceptionAddressRegister() to getExceptionPointerRegister() for ↵Lang Hames2012-02-141-1/+1
| | | | | | consistency with setExceptionPointerRegister(...). llvm-svn: 150460
* Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling2012-02-131-0/+6
| | | | | | | marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. llvm-svn: 150437
* [unwind removal] Remove all of the code for the dead 'unwind' instruction. ThereBill Wendling2012-02-061-3/+0
| | | | | | | were no 'unwind' instructions being generated before this, so this is in effect a no-op. llvm-svn: 149906
* SwitchInst refactoring.Stepan Dyatkovskiy2012-02-011-6/+6
| | | | | | | | | | | | | | | | | The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want. What was done: 1. Changed semantics of index inside the getCaseValue method: getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous. 2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned. 3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment. 4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst. 4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor. 4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor. Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang. llvm-svn: 149481
* Remove the now-dead llvm.eh.exception and llvm.eh.selector intrinsics.Bill Wendling2012-01-311-37/+0
| | | | llvm-svn: 149331
* continue making the world safe for ConstantDataVector. At this point,Chris Lattner2012-01-271-1/+1
| | | | | | | we should (theoretically optimize and codegen ConstantDataVector as well as ConstantVector. llvm-svn: 149116
* eliminate the Constant::getVectorElements method. There are better (andChris Lattner2012-01-261-13/+4
| | | | | | | more robust) ways to do what it was doing now. Also, add static methods for decoding a ShuffleVector mask. llvm-svn: 149028
* Use the right method to get the # elements in a CDS.Chris Lattner2012-01-251-1/+1
| | | | llvm-svn: 148897
* add more support for ConstantDataSequentialChris Lattner2012-01-241-2/+19
| | | | llvm-svn: 148802
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-5/+1
| | | | llvm-svn: 148578
* Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get ↵Pete Cooper2012-01-171-2/+3
| | | | | | checked for legalisation llvm-svn: 148275
* Changed intrinsic ID operand to a target constant as its not used in any ↵Pete Cooper2012-01-161-1/+1
| | | | | | arithmetic so should not be checked in legalisation llvm-svn: 148228
* Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper2012-01-041-11/+24
| | | | | | are commuted in the shuffle mask. llvm-svn: 147527
* Turn a few more inline asm errors into "emitErrors" instead of fatal errors.Chris Lattner2012-01-031-9/+21
| | | | | | | | | | | | | | | | | | Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. llvm-svn: 147502
* Remove the restriction that target intrinsics can only involve legal types. ↵Owen Anderson2012-01-031-8/+0
| | | | | | Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. llvm-svn: 147472
* Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.Jakub Staszak2011-12-201-2/+2
| | | | llvm-svn: 146986
* Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. ↵Owen Anderson2011-12-151-0/+22
| | | | | | These are already marked as illegal by default. llvm-svn: 146623
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter ↵Owen Anderson2011-12-081-13/+34
| | | | | | can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed. llvm-svn: 146193
* Teach SelectionDAG to match more calls to libm functions onto existing ↵Owen Anderson2011-12-081-0/+47
| | | | | | SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. llvm-svn: 146171
* Add support for vectors of pointers.Nadav Rotem2011-12-051-1/+1
| | | | llvm-svn: 145801
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-8/+12
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Remove dead llvm.eh.sjlj.dispatchsetup intrinsic.Bill Wendling2011-11-281-5/+0
| | | | llvm-svn: 145263
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