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* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-2/+3
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Instead of passing in an unsigned value for the optimization level, use an enum,Bill Wendling2009-04-291-2/+2
| | | | | | | which better identifies what the optimization is doing. And is more flexible for future uses. llvm-svn: 70440
* Second attempt:Bill Wendling2009-04-291-2/+2
| | | | | | | | | | | | Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'll change the JIT with a follow-up patch. llvm-svn: 70343
* r70270 isn't ready yet. Back this out. Sorry for the noise.Bill Wendling2009-04-281-2/+2
| | | | llvm-svn: 70275
* Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want toBill Wendling2009-04-281-2/+2
| | | | | | | | | | | use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure if it's necessary to change it there... llvm-svn: 70270
* In the list-burr's pseudo two-addr dependency heuristics, don'tDan Gohman2009-04-161-0/+10
| | | | | | | | | add dependencies on nodes with exactly one successor which is a COPY_TO_REGCLASS node. In the case that the copy is coalesced away, the dependence should be on the user of the copy, rather than the copy itself. llvm-svn: 69309
* Handle SUBREG_TO_REG instructions with the same heuristicsDan Gohman2009-04-161-5/+7
| | | | | | as INSERT_SUBREG instructions in the list-burr scheduler. llvm-svn: 69308
* Minor compile-time optimization; don't bother checkingDan Gohman2009-03-241-1/+1
| | | | | | | canClobberPhysRegDefs if the successor node doesn't clobber any physical registers. llvm-svn: 67587
* Add a pre-pass to the burr-list scheduler which makes adjustments toDan Gohman2009-03-241-0/+120
| | | | | | | | | help out the register pressure reduction heuristics in the case of nodes with multiple uses. Currently this uses very conservative heuristics, so it doesn't have a broad impact, but in cases where it does help it can make a big difference. llvm-svn: 67586
* When unfolding a load during scheduling, the new operator node hasDan Gohman2009-03-231-3/+6
| | | | | | | | | | a data dependency on the load node, so it really needs a data-dependence edge to the load node, even if the load previously existed. And add a few comments. llvm-svn: 67554
* Fix canClobberPhysRegDefs to check all SDNodes grouped togetherDan Gohman2009-03-231-14/+19
| | | | | | | in an SUnit, instead of just the first one. This fix is needed by some upcoming scheduler changes. llvm-svn: 67531
* For inline asm output operand that matches an input. Encode the input ↵Evan Cheng2009-03-201-1/+1
| | | | | | operand index in the high bits. llvm-svn: 67387
* Fix a typo in a comment.Dan Gohman2009-03-121-1/+1
| | | | llvm-svn: 66843
* Fix ScheduleDAGRRList::CopyAndMoveSuccessors' handling of nodesDan Gohman2009-03-061-7/+7
| | | | | | | | | | | with multiple chain operands. This can occur when the scheduler has added chain operands to a node that already has a chain operand, in order to handle physical register dependencies. This fixes an llvm-gcc bootstrap failure on x86-64 introduced in r66058. llvm-svn: 66240
* Fix PR3701. 1. X86 target renamed eflags register to flags. This matches ↵Evan Cheng2009-03-041-25/+54
| | | | | | what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. llvm-svn: 65996
* Oops. Last second clean up messed things up.Evan Cheng2009-02-121-2/+3
| | | | llvm-svn: 64373
* Replace one of burr scheduling heuristic with something more sensible. Now ↵Evan Cheng2009-02-121-18/+4
| | | | | | calcMaxScratches simply compute the number of true data dependencies. This actually improve a couple of tests in dejagnu suite as many tests in llvm nightly test suite. llvm-svn: 64369
* Fix a comment.Dan Gohman2009-02-111-2/+2
| | | | llvm-svn: 64328
* Don't use special heuristics for nodes with no data predecessorsDan Gohman2009-02-111-8/+9
| | | | | | | unless they actually have data successors, and likewise for nodes with no data successors unless they actually have data precessors. llvm-svn: 64327
* Delete the heuristic for non-livein CopyFromReg nodes. Non-liveinnessDan Gohman2009-02-111-11/+0
| | | | | | | | | is determined by whether the node has a Flag operand. However, if the node does have a Flag operand, it will be glued to its register's def, so the heuristic would end up spuriously applying to whatever node is the def. llvm-svn: 64319
* When scheduling a block in parts, keep track of the overallDan Gohman2009-02-111-4/+4
| | | | | | | | | | | instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. llvm-svn: 64288
* Factor out more code for computing register live-range informationforDan Gohman2009-02-101-22/+42
| | | | | | | | | | | scheduling, and generalize is so that preserves state across scheduling regions. This fixes incorrect live-range information around terminators and labels, which are effective region boundaries. In place of looking for terminators to anchor inter-block dependencies, introduce special entry and exit scheduling units for this purpose. llvm-svn: 64254
* Fix PR3457: Ignore control successors when looking for closest scheduled ↵Evan Cheng2009-02-101-1/+1
| | | | | | successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated. llvm-svn: 64210
* Move ScheduleDAGSDNodes.h to be a private header. Front-endsDan Gohman2009-02-061-1/+1
| | | | | | | that previously included this header should include SchedulerRegistry.h instead. llvm-svn: 63937
* Make a few things const, fix some comments, and simplifyDan Gohman2009-01-291-16/+8
| | | | | | some assertions. llvm-svn: 63328
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-151-15/+13
| | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. llvm-svn: 62275
* The list-td and list-tdrr schedulers don't yet support physregDan Gohman2009-01-131-1/+5
| | | | | | | | | | | scheduling dependencies. Add assertion checks to help catch this. It appears the Mips target defaults to list-td, and it has a regression test that uses a physreg dependence. Such code was liable to be miscompiled, and now evokes an assertion failure. llvm-svn: 62177
* Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical ↵Evan Cheng2009-01-121-27/+31
| | | | | | | | register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency. Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet. llvm-svn: 62074
* Minor debug output tweak.Evan Cheng2009-01-091-2/+2
| | | | llvm-svn: 62005
* Remove redundant 'else's. No functionality change.Dan Gohman2009-01-071-7/+6
| | | | llvm-svn: 61891
* Update these argument lists for the isNormalMemoryDan Gohman2009-01-061-3/+6
| | | | | | argument. This doesn't affect current functionality. llvm-svn: 61779
* Use a latency value of 0 for the artificial edges inserted byDan Gohman2009-01-061-1/+1
| | | | | | | | | | | | AddPseudoTwoAddrDeps. This lets the scheduling infrastructure avoid recalculating node heights. In very large testcases this was a major bottleneck. Thanks to Roman Levenstein for finding this! As a side effect, fold-pcmpeqd-0.ll is now scheduled better and it no longer requires spilling on x86-32. llvm-svn: 61778
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-051-2/+0
| | | | llvm-svn: 61715
* CommuteNodesToReducePressure() is now removed.Dan Gohman2009-01-031-1/+0
| | | | llvm-svn: 61612
* Remove the code from the scheduler that commuted two-addressDan Gohman2009-01-031-54/+0
| | | | | | | | | | | | | | instructions to avoid copies, because TwoAddressInstructionPass also does this optimization. The scheduler's version didn't account for live-out values, which resulted in spurious commutes and missed opportunities. Now, TwoAddressInstructionPass handles all the opportunities, instead of just those that the scheduler missed. The result is usually the same, though there are occasional trivial differences resulting from the avoidance of spurious commutes. llvm-svn: 61611
* Rename BuildSchedUnits to BuildSchedGraph, and refactor theDan Gohman2008-12-231-2/+2
| | | | | | code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions. llvm-svn: 61376
* Fix some register-alias-related bugs in the post-RA scheduler livenessDan Gohman2008-12-161-37/+30
| | | | | | | | | | | | | | computation code. Also, avoid adding output-depenency edges when both defs are dead, which frequently happens with EFLAGS defs. Compute Depth and Height lazily, and always in terms of edge latency values. For the schedulers that don't care about latency, edge latencies are set to 1. Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array. These are all subsumed by the Depth and Height fields. llvm-svn: 61073
* Make addPred and removePred return void, since the return value is notDan Gohman2008-12-161-4/+4
| | | | | | currently used by anything. llvm-svn: 61066
* Rewrite the SDep class, and simplify some of the related code.Dan Gohman2008-12-091-118/+134
| | | | | | | | | | | | | | | | | The Cost field is removed. It was only being used in a very limited way, to indicate when the scheduler should attempt to protect a live register, and it isn't really needed to do that. If we ever want the scheduler to start inserting copies in non-prohibitive situations, we'll have to rethink some things anyway. A Latency field is added. Instead of giving each node a single fixed latency, each edge can have its own latency. This will eventually be used to model various micro-architecture properties more accurately. The PointerIntPair class and an internal union are now used, which reduce the overall size. llvm-svn: 60806
* Make debug output more informative.Dan Gohman2008-12-041-1/+1
| | | | llvm-svn: 60524
* Initial support for anti-dependence breaking. Currently this code does notDan Gohman2008-11-251-238/+26
| | | | | | | | | introduce any new spilling; it just uses unused registers. Refactor the SUnit topological sort code out of the RRList scheduler and make use of it to help with the post-pass scheduler. llvm-svn: 59999
* Check in the rest of this change. The isAntiDep flag needs to be passedDan Gohman2008-11-241-1/+1
| | | | | | | to removePred because an SUnit can both data-depend and anti-depend on the same SUnit. llvm-svn: 59969
* Add a flag to SDep for tracking which edges are anti-dependence edges.Dan Gohman2008-11-211-4/+4
| | | | llvm-svn: 59785
* Rename SDep's isSpecial to isArtificial, to make this field a littleDan Gohman2008-11-211-20/+20
| | | | | | less mysterious. llvm-svn: 59782
* Remove the CycleBound computation code from the ScheduleDAGRRListDan Gohman2008-11-211-58/+5
| | | | | | | | | | | | | schedulers. This doesn't have much immediate impact because targets that use these schedulers by default don't yet provide pipeline information. This code also didn't have the benefit of register pressure information. Also, removing it will avoid problems with list-burr suddenly starting to do latency-oriented scheduling on x86 when we start providing pipeline data, which would increase spilling. llvm-svn: 59775
* Change these schedulers to not emit no-ops. It turns out thatDan Gohman2008-11-211-6/+2
| | | | | | | | | the RR scheduler actually does look at latency values, but it doesn't use a hazard recognizer so it has no way to know when a no-op is needed, as opposed to just stalling and incrementing the cycle count. llvm-svn: 59759
* Remove a remnant of list-burr's fast mode.Dan Gohman2008-11-201-20/+0
| | | | llvm-svn: 59702
* Factor out the SethiUllman numbering logic from the list-burr andDan Gohman2008-11-201-159/+47
| | | | | | list-tdrr schedulers into a common base class. llvm-svn: 59701
* Remove the "fast" form of the list-burr scheduler, and use theDan Gohman2008-11-201-68/+9
| | | | | | | | | dedicated "fast" scheduler in -fast mode instead, which is faster. This speeds up llc -fast by a few percent on some testcases -- the speedup only happens for code not handled by fast-isel. llvm-svn: 59700
* Facter AddPseudoTwoAddrDeps and associated infrasructure out ofDan Gohman2008-11-201-43/+60
| | | | | | | the list-burr scheduler so that it can be used by the list-tdrr scheduler too. llvm-svn: 59698
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