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authorDan Gohman <gohman@apple.com>2009-03-23 16:23:01 +0000
committerDan Gohman <gohman@apple.com>2009-03-23 16:23:01 +0000
commita366da1bf795449f3b34af4e15e584460cb23658 (patch)
treeba7cad61c5c1eec4bc1b1ca6bca46cce933263d3 /llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
parentd4eca014e0802e12fdd561eeedee0c9388fc98e7 (diff)
downloadbcm5719-llvm-a366da1bf795449f3b34af4e15e584460cb23658.tar.gz
bcm5719-llvm-a366da1bf795449f3b34af4e15e584460cb23658.zip
Fix canClobberPhysRegDefs to check all SDNodes grouped together
in an SUnit, instead of just the first one. This fix is needed by some upcoming scheduler changes. llvm-svn: 67531
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp33
1 files changed, 19 insertions, 14 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 7ae56d78499..8e449971db3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1199,21 +1199,26 @@ static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
assert(ImpDefs && "Caller should check hasPhysRegDefs");
- const unsigned *SUImpDefs =
- TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
- if (!SUImpDefs)
- return false;
- for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
- MVT VT = N->getValueType(i);
- if (VT == MVT::Flag || VT == MVT::Other)
+ for (const SDNode *SUNode = SU->getNode(); SUNode;
+ SUNode = SUNode->getFlaggedNode()) {
+ if (!SUNode->isMachineOpcode())
continue;
- if (!N->hasAnyUseOfValue(i))
- continue;
- unsigned Reg = ImpDefs[i - NumDefs];
- for (;*SUImpDefs; ++SUImpDefs) {
- unsigned SUReg = *SUImpDefs;
- if (TRI->regsOverlap(Reg, SUReg))
- return true;
+ const unsigned *SUImpDefs =
+ TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
+ if (!SUImpDefs)
+ return false;
+ for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
+ MVT VT = N->getValueType(i);
+ if (VT == MVT::Flag || VT == MVT::Other)
+ continue;
+ if (!N->hasAnyUseOfValue(i))
+ continue;
+ unsigned Reg = ImpDefs[i - NumDefs];
+ for (;*SUImpDefs; ++SUImpDefs) {
+ unsigned SUReg = *SUImpDefs;
+ if (TRI->regsOverlap(Reg, SUReg))
+ return true;
+ }
}
}
return false;
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