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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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* Introducing a new method of tracking register pressure. We can'tAndrew Trick2011-02-041-111/+62
* Remove a temporary workaround for a lencod miscompile. Depends on the fix in ...Andrew Trick2011-01-271-2/+0
* Temporarily workaround JM/lencod miscompile (SIGSEGV).Andrew Trick2011-01-241-0/+2
* Enable support for precise scheduling of the instruction selectionAndrew Trick2011-01-211-1/+1
* Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick2011-01-211-29/+31
* Selection DAG scheduler register pressure heuristic fixes.Andrew Trick2011-01-201-8/+27
* Support for precise scheduling of the instruction selection DAG,Andrew Trick2011-01-141-537/+663
* Minor cleanup related to my latest scheduler changes.Andrew Trick2010-12-241-3/+5
* Fix a few cases where the scheduler is not checking for phys reg copies. The ...Andrew Trick2010-12-241-3/+10
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-60/+367
* flags -> glue for selectiondagChris Lattner2010-12-231-6/+6
* Reorganize ListScheduleBottomUp in preparation for modeling machine cycles an...Andrew Trick2010-12-231-130/+153
* Converted LiveRegCycles to LiveRegGens. It's easier to work with and allows m...Andrew Trick2010-12-231-17/+18
* In CheckForLiveRegDef use TRI->getOverlaps.Andrew Trick2010-12-231-6/+9
* Fixes PR8823: add-with-overflow-128.llAndrew Trick2010-12-231-12/+33
* In DelayForLiveRegsBottomUp, handle instructions that read and writeAndrew Trick2010-12-211-15/+4
* whitespaceAndrew Trick2010-12-211-42/+42
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-5/+5
* Fix a bug in the scheduler's handling of "unspillable" vregs.Chris Lattner2010-12-201-1/+14
* the result of CheckForLiveRegDef is dead, remove it.Chris Lattner2010-12-201-12/+8
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-031-0/+8
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-291-24/+69
* The "excess register pressure" returned by HighRegPressure() is not accurate ...Evan Cheng2010-07-261-41/+20
* Pacify gcc-4.5 which wrongly thinks that RExcess (passed as the Excess parame...Duncan Sands2010-07-261-1/+2
* Add comments.Evan Cheng2010-07-251-4/+16
* Fix crashes when scheduling a CopyToReg node -- getMachineOpcode asserts onBob Wilson2010-07-251-2/+2
* Add an ILP scheduler. This is a register pressure aware scheduler that'sEvan Cheng2010-07-241-10/+72
* - Allow target to specify when is register pressure "too high". In most cases,Evan Cheng2010-07-231-56/+124
* Re-apply r109079 with fix.Evan Cheng2010-07-221-28/+26
* Revert r109079, which broke a lot of CodeGen tests.Owen Anderson2010-07-221-25/+27
* Initialize RegLimit only when register pressure is being tracked.Evan Cheng2010-07-221-27/+25
* More register pressure aware scheduling work.Evan Cheng2010-07-211-81/+84
* Teach bottom up pre-ra scheduler to track register pressure. Work in progress.Evan Cheng2010-07-211-15/+229
* Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola2010-06-291-1/+1
* Use `llvm::next' instead of `next' to make VC++ 2010 happy.Oscar Fuentes2010-05-301-1/+1
* Fix some latency computation bugs: if the use is not a machine opcode do not ...Evan Cheng2010-05-281-1/+12
* Eliminate the use of PriorityQueue and just use a std::vector,Dan Gohman2010-05-261-7/+18
* Delete an unused function.Dan Gohman2010-05-261-2/+0
* Change push_all to a non-virtual function and implement it in theDan Gohman2010-05-261-5/+0
* Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.Evan Cheng2010-05-211-1/+1
* Allow targets more controls on what nodes are scheduled by reg pressure, what...Evan Cheng2010-05-201-2/+4
* Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng2010-05-201-25/+92
* Three changes:Chris Lattner2010-04-071-5/+7
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-7/+7
* When the scheduler unfold a load folding instruction it move some of the pred...Evan Cheng2010-02-051-2/+10
* Remove the '-disable-scheduling' flag and replace it with the 'source' option ofBill Wendling2010-01-231-14/+56
* The previous code could potentially cause a cycle. Allow ordering w.r.t. a 0 ...Bill Wendling2010-01-061-2/+2
* Only check the ordering if there is an ordering for each nodes.Bill Wendling2010-01-061-2/+2
* Add a semi-primitive form of scheduling via the "SDNode ordering" to theBill Wendling2010-01-051-0/+12
* Change errs() to dbgs().David Greene2010-01-051-14/+14
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