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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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* Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola2010-06-291-1/+1
| | | | | | | | | of getPhysicalRegisterRegClass with it. If we want to make a copy (or estimate its cost), it is better to use the smallest class as more efficient operations might be possible. llvm-svn: 107140
* Use `llvm::next' instead of `next' to make VC++ 2010 happy.Oscar Fuentes2010-05-301-1/+1
| | | | llvm-svn: 105168
* Fix some latency computation bugs: if the use is not a machine opcode do not ↵Evan Cheng2010-05-281-1/+12
| | | | | | just return zero. llvm-svn: 105061
* Eliminate the use of PriorityQueue and just use a std::vector,Dan Gohman2010-05-261-7/+18
| | | | | | | | implementing pop with a linear search for a "best" element. The priority queue was a neat idea, but in practice the comparison functions depend on dynamic information. llvm-svn: 104718
* Delete an unused function.Dan Gohman2010-05-261-2/+0
| | | | llvm-svn: 104716
* Change push_all to a non-virtual function and implement it in theDan Gohman2010-05-261-5/+0
| | | | | | base class, since all the implementations are the same. llvm-svn: 104659
* Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.Evan Cheng2010-05-211-1/+1
| | | | llvm-svn: 104306
* Allow targets more controls on what nodes are scheduled by reg pressure, ↵Evan Cheng2010-05-201-2/+4
| | | | | | what for latency in hybrid mode. llvm-svn: 104293
* Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng2010-05-201-25/+92
| | | | | | | | | pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot of long latency instructions so a strict register pressure reduction scheduler does not work well. Early experiments show this speeds up some NEON loops by over 30%. llvm-svn: 104216
* Three changes:Chris Lattner2010-04-071-5/+7
| | | | | | | | | | | | | | | 1. Introduce some enums and accessors in the InlineAsm class that eliminate a ton of magic numbers when handling inline asm SDNode. 2. Add a new MDNodeSDNode selection dag node type that holds a MDNode (shocking!) 3. Add a new argument to ISD::INLINEASM nodes that hold !srcloc metadata, propagating it to the instruction emitter, which drops it. No functionality change. llvm-svn: 100605
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-7/+7
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* When the scheduler unfold a load folding instruction it move some of the ↵Evan Cheng2010-02-051-2/+10
| | | | | | | | predecessors to the unfolded load. It decides what gets moved to the load by checking whether the new load is using the predecessor as an operand. The check neglects the cases whether the predecessor is a flagged scheduling unit. rdar://7604000 llvm-svn: 95339
* Remove the '-disable-scheduling' flag and replace it with the 'source' option ofBill Wendling2010-01-231-14/+56
| | | | | | | | | the '-pre-RA-sched' flag. It actually makes more sense to do it this way. Also, keep track of the SDNode ordering by default. Eventually, we would like to make this ordering a way to break a "tie" in the scheduler. However, doing that now breaks the "CodeGen/X86/abi-isel.ll" test for 32-bit Linux. llvm-svn: 94308
* The previous code could potentially cause a cycle. Allow ordering w.r.t. a 0 ↵Bill Wendling2010-01-061-2/+2
| | | | | | order. llvm-svn: 92810
* Only check the ordering if there is an ordering for each nodes.Bill Wendling2010-01-061-2/+2
| | | | llvm-svn: 92807
* Add a semi-primitive form of scheduling via the "SDNode ordering" to theBill Wendling2010-01-051-0/+12
| | | | | | bottom-up scheduler. We prefer the lower order number. llvm-svn: 92806
* Change errs() to dbgs().David Greene2010-01-051-14/+14
| | | | llvm-svn: 92576
* Remove includes of Support/Compiler.h that are no longer needed after theNick Lewycky2009-10-251-1/+0
| | | | | | VISIBILITY_HIDDEN removal. llvm-svn: 85043
* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-251-3/+2
| | | | | | | Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. llvm-svn: 85042
* The ScheduleDAG framework now requires an AliasAnalysis argument, thoughDan Gohman2009-10-091-1/+1
| | | | | | it isn't needed in the ScheduleDAGSDNodes schedulers. llvm-svn: 83691
* Silence comparison always false warning in -Asserts mode.Reid Kleckner2009-09-301-4/+4
| | | | llvm-svn: 83164
* Fix integer overflow in instruction scheduling. This can happen if we haveReid Kleckner2009-09-301-4/+5
| | | | | | | | | | basic blocks that are so long that their size overflows a short. Also assert that overflow does not happen in the future, as requested by Evan. This fixes PR4401. llvm-svn: 83159
* eliminate uses of cerr()Chris Lattner2009-08-231-4/+4
| | | | llvm-svn: 79834
* remove a few DOUTs here and there.Chris Lattner2009-08-231-15/+16
| | | | llvm-svn: 79832
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-5/+5
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-10/+10
| | | | | | own struct type. llvm-svn: 78610
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-2/+2
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-2/+3
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Instead of passing in an unsigned value for the optimization level, use an enum,Bill Wendling2009-04-291-2/+2
| | | | | | | which better identifies what the optimization is doing. And is more flexible for future uses. llvm-svn: 70440
* Second attempt:Bill Wendling2009-04-291-2/+2
| | | | | | | | | | | | Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'll change the JIT with a follow-up patch. llvm-svn: 70343
* r70270 isn't ready yet. Back this out. Sorry for the noise.Bill Wendling2009-04-281-2/+2
| | | | llvm-svn: 70275
* Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want toBill Wendling2009-04-281-2/+2
| | | | | | | | | | | use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure if it's necessary to change it there... llvm-svn: 70270
* In the list-burr's pseudo two-addr dependency heuristics, don'tDan Gohman2009-04-161-0/+10
| | | | | | | | | add dependencies on nodes with exactly one successor which is a COPY_TO_REGCLASS node. In the case that the copy is coalesced away, the dependence should be on the user of the copy, rather than the copy itself. llvm-svn: 69309
* Handle SUBREG_TO_REG instructions with the same heuristicsDan Gohman2009-04-161-5/+7
| | | | | | as INSERT_SUBREG instructions in the list-burr scheduler. llvm-svn: 69308
* Minor compile-time optimization; don't bother checkingDan Gohman2009-03-241-1/+1
| | | | | | | canClobberPhysRegDefs if the successor node doesn't clobber any physical registers. llvm-svn: 67587
* Add a pre-pass to the burr-list scheduler which makes adjustments toDan Gohman2009-03-241-0/+120
| | | | | | | | | help out the register pressure reduction heuristics in the case of nodes with multiple uses. Currently this uses very conservative heuristics, so it doesn't have a broad impact, but in cases where it does help it can make a big difference. llvm-svn: 67586
* When unfolding a load during scheduling, the new operator node hasDan Gohman2009-03-231-3/+6
| | | | | | | | | | a data dependency on the load node, so it really needs a data-dependence edge to the load node, even if the load previously existed. And add a few comments. llvm-svn: 67554
* Fix canClobberPhysRegDefs to check all SDNodes grouped togetherDan Gohman2009-03-231-14/+19
| | | | | | | in an SUnit, instead of just the first one. This fix is needed by some upcoming scheduler changes. llvm-svn: 67531
* For inline asm output operand that matches an input. Encode the input ↵Evan Cheng2009-03-201-1/+1
| | | | | | operand index in the high bits. llvm-svn: 67387
* Fix a typo in a comment.Dan Gohman2009-03-121-1/+1
| | | | llvm-svn: 66843
* Fix ScheduleDAGRRList::CopyAndMoveSuccessors' handling of nodesDan Gohman2009-03-061-7/+7
| | | | | | | | | | | with multiple chain operands. This can occur when the scheduler has added chain operands to a node that already has a chain operand, in order to handle physical register dependencies. This fixes an llvm-gcc bootstrap failure on x86-64 introduced in r66058. llvm-svn: 66240
* Fix PR3701. 1. X86 target renamed eflags register to flags. This matches ↵Evan Cheng2009-03-041-25/+54
| | | | | | what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. llvm-svn: 65996
* Oops. Last second clean up messed things up.Evan Cheng2009-02-121-2/+3
| | | | llvm-svn: 64373
* Replace one of burr scheduling heuristic with something more sensible. Now ↵Evan Cheng2009-02-121-18/+4
| | | | | | calcMaxScratches simply compute the number of true data dependencies. This actually improve a couple of tests in dejagnu suite as many tests in llvm nightly test suite. llvm-svn: 64369
* Fix a comment.Dan Gohman2009-02-111-2/+2
| | | | llvm-svn: 64328
* Don't use special heuristics for nodes with no data predecessorsDan Gohman2009-02-111-8/+9
| | | | | | | unless they actually have data successors, and likewise for nodes with no data successors unless they actually have data precessors. llvm-svn: 64327
* Delete the heuristic for non-livein CopyFromReg nodes. Non-liveinnessDan Gohman2009-02-111-11/+0
| | | | | | | | | is determined by whether the node has a Flag operand. However, if the node does have a Flag operand, it will be glued to its register's def, so the heuristic would end up spuriously applying to whatever node is the def. llvm-svn: 64319
* When scheduling a block in parts, keep track of the overallDan Gohman2009-02-111-4/+4
| | | | | | | | | | | instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. llvm-svn: 64288
* Factor out more code for computing register live-range informationforDan Gohman2009-02-101-22/+42
| | | | | | | | | | | scheduling, and generalize is so that preserves state across scheduling regions. This fixes incorrect live-range information around terminators and labels, which are effective region boundaries. In place of looking for terminators to anchor inter-block dependencies, introduce special entry and exit scheduling units for this purpose. llvm-svn: 64254
* Fix PR3457: Ignore control successors when looking for closest scheduled ↵Evan Cheng2009-02-101-1/+1
| | | | | | successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated. llvm-svn: 64210
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