summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Experimental post-pass scheduling support. Post-pass schedulingDan Gohman2008-11-191-717/+0
| | | | | | | | | | | | | | | | | is currently off by default, and can be enabled with -disable-post-RA-scheduler=false. This doesn't have a significant impact on most code yet because it doesn't yet do anything to address anti-dependencies and it doesn't attempt to disambiguate memory references. Also, several popular targets don't have pipeline descriptions yet. The majority of the changes here are splitting the SelectionDAG-specific code out of ScheduleDAG, so that ScheduleDAG can be moved to libLLVMCodeGen.a. The interface between ScheduleDAG-using code and the rest of the scheduling code is somewhat rough and will evolve. llvm-svn: 59676
* For post-regalloc scheduling, remove the instructions from the blockDan Gohman2008-11-141-0/+6
| | | | | | before re-inserting them. llvm-svn: 59281
* Initial support for carrying MachineInstrs in SUnits.Dan Gohman2008-11-141-0/+10
| | | | llvm-svn: 59278
* Remove the FlaggedNodes member from SUnit. Instead of requiring each SUnitDan Gohman2008-11-131-2/+7
| | | | | | | | | | to carry a SmallVector of flagged nodes, just calculate the flagged nodes dynamically when they are needed. The local-liveness change is due to a trivial scheduling change where the scheduler arbitrary decision differently. llvm-svn: 59273
* Make the Node member of SUnit private, and add accessors.Dan Gohman2008-11-131-3/+3
| | | | llvm-svn: 59264
* Change ScheduleDAG's DAG member from a reference to a pointer, to prepareDan Gohman2008-11-131-2/+2
| | | | | | for the possibility of scheduling without a SelectionDAG being present. llvm-svn: 59263
* Next round of earlyclobber handling. Approach theDale Johannesen2008-09-241-18/+5
| | | | | | | | | | RA problem by expanding the live interval of an earlyclobber def back one slot. Remove overlap-earlyclobber throughout. Remove earlyclobber bits and their handling from live internals. llvm-svn: 56539
* Add a bit to mark operands of asm's that conflictDale Johannesen2008-09-171-5/+18
| | | | | | | | | with an earlyclobber operand elsewhere. Propagate this bit and the earlyclobber bit through SDISel. Change linear-scan RA not to allocate regs in a way that conflicts with an earlyclobber. See also comments. llvm-svn: 56290
* When converting a CopyFromReg to a copy instruction, use the register class ↵Evan Cheng2008-09-161-5/+24
| | | | | | of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes. llvm-svn: 56258
* Reverting r56249. On further investigation, this functionality isn't needed.Bill Wendling2008-09-161-2/+3
| | | | | | Apologies for the thrashing. llvm-svn: 56251
* - Change "ExternalSymbolSDNode" to "SymbolSDNode".Bill Wendling2008-09-161-3/+2
| | | | | | | | | | - Add linkage to SymbolSDNode (default to external). - Change ISD::ExternalSymbol to ISD::Symbol. - Change ISD::TargetExternalSymbol to ISD::TargetSymbol These changes pave the way to allowing SymbolSDNodes with non-external linkage. llvm-svn: 56249
* Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* andDan Gohman2008-09-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | ConstantFP* instead of APInt and APFloat directly. This reduces the amount of time to create ConstantSDNode and ConstantFPSDNode nodes when ConstantInt* and ConstantFP* respectively are already available, as is the case in SelectionDAGBuild.cpp. Also, it reduces the amount of time to legalize constants into constant pools, and the amount of time to add ConstantFP operands to MachineInstrs, due to eliminating ConstantInt::get and ConstantFP::get calls. It increases the amount of work needed to create new constants in cases where the client doesn't already have a ConstantInt* or ConstantFP*, such as legalize expanding 64-bit integer constants to 32-bit constants. And it adds a layer of indirection for the accessor methods. But these appear to be outweight by the benefits in most cases. It will also make it easier to make ConstantSDNode and ConstantFPNode more consistent with ConstantInt and ConstantFP. llvm-svn: 56162
* Pass "earlyclobber" bit through to machineDale Johannesen2008-09-121-0/+7
| | | | | | | representation; coalescer and RA need to know about it. No functional change. llvm-svn: 56161
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-5/+6
| | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
* Move the code that inserts copies for function livein registersDan Gohman2008-09-051-102/+0
| | | | | | | | | out of ScheduleDAGEmit.cpp and into SelectionDAGISel.cpp. This allows it to be run exactly once per function, even if multiple SelectionDAG iterations happen in the entry block, as may happen with FastISel. llvm-svn: 55863
* Revert r55817. It broke PIC. FastISel will need to find a differentDan Gohman2008-09-051-3/+1
| | | | | | approach here. llvm-svn: 55842
* In FastISel mode, the scheduler may be invoked multiple timesDan Gohman2008-09-051-1/+3
| | | | | | | in the same block. Fix the entry-block handling to only run at at the beginning of the entry block, and not any other times. llvm-svn: 55817
* Separate MachineInstr-emitting routines from actual schedulingDan Gohman2008-09-031-0/+771
routines and move them into a separate file, ScheduleDAGEmit.cpp. llvm-svn: 55699
OpenPOWER on IntegriCloud