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path: root/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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* [LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHGAlex Bradbury2020-06-251-1/+13
* [AArch64][FPenv] Update chain of int to fp conversionDiogo Sampaio2020-02-181-2/+8
* [LegalizeTypes] Remove untested code from ExpandIntOp_UINT_TO_FPCraig Topper2020-01-141-70/+2
* [LegalizeIntegerTypes][X86] Add support for expanding input of STRICT_SINT_TO...Craig Topper2020-01-131-6/+30
* [Intrinsic] Add fixed point division intrinsics.Bevin Hansson2020-01-081-2/+82
* [NFC] Fix trivial typos in commentsJames Henderson2020-01-061-1/+1
* [FPEnv][LegalizeTypes][LegalizeDAG][AArch64] Few fixes/improvements for legal...Craig Topper2019-12-171-0/+12
* [NFC] Use SelectionDAG::getMemBasePlusOffset() instead of getNode(ISD::ADD)Alex Richardson2019-12-131-6/+3
* [LegalizeTypes] Bugfixes for big-endian targets when handling BITCASTsMikael Holmen2019-12-101-2/+15
* [FPEnv] Constrained FCmp intrinsicsUlrich Weigand2019-12-071-4/+17
* [LegalizeTypes][X86] Add ExpandIntegerResult support for STRICT_FP_TO_SINT/ST...Craig Topper2019-11-271-6/+20
* [Codegen][ARM] Add addressing modes from masked loads and storesDavid Green2019-11-261-7/+9
* [TargetLowering] Merge ExpandChainLibCall with makeLibCallCraig Topper2019-11-251-10/+13
* [SelectionDAG] Merge the two identical ExpandChainLibCall methods from Legali...Craig Topper2019-11-181-2/+2
* [LegalizeTypes] Remove SoftenFloat handling from ExpandIntRes_LLROUND_LLRINT ...Craig Topper2019-11-171-9/+0
* [LegalizeTypes][X86] Add support for expanding the result type of STRICT_LLRO...Craig Topper2019-11-171-3/+18
* [LegalizeTypes] When expanding the integer result of LLROUND/LLRINT, also cal...Craig Topper2019-11-171-0/+6
* [LegalizeTypes] Remove PromoteFloat support form ExpandIntRes_LLROUND_LLRINT.Craig Topper2019-11-171-5/+6
* [LegalizeTypes] Merge ExpandIntRes_LLROUND and ExpandIntRes_LLRINT into one f...Craig Topper2019-11-171-42/+30
* [SelectionDAG] Enable lowering unordered atomics loads w/LoadSDNode (and stor...Philip Reames2019-10-291-0/+25
* [LegalizeTypes] When promoting BITREVERSE/BSWAP don't take the shift amount i...Craig Topper2019-10-271-10/+9
* [CodeGen][SelectionDAG] Fix tiny bug in ExpandIntRes_UADDSUBOItay Bookstein2019-10-251-9/+22
* [AArch64][SVE] Add SPLAT_VECTOR ISD NodeGraham Hunter2019-10-181-0/+28
* [Codegen] Alter the default promotion for saturating adds and subsDavid Green2019-10-181-33/+69
* Revert 374373: [Codegen] Alter the default promotion for saturating adds and ...David Green2019-10-111-61/+31
* [Codegen] Alter the default promotion for saturating adds and subsDavid Green2019-10-101-31/+61
* [Intrinsic] Add the llvm.umul.fix.sat intrinsicBjorn Pettersson2019-09-071-18/+66
* [CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIXBjorn Pettersson2019-09-031-49/+19
* [CodeGen] Refactor DAGTypeLegalizer::ExpandIntRes_MULFIX. NFCBjorn Pettersson2019-08-311-87/+92
* [FPEnv] Add fptosi and fptoui constrained intrinsics.Kevin P. Neal2019-08-281-2/+18
* [TargetLowering] Remove optional arguments passing to makeLibCallShiva Chen2019-08-221-12/+33
* [SelectionDAG] Extend base addressing modes supported by MGATHER/MSCATTERCullen Rhodes2019-08-061-5/+13
* [SelectionDAG] Simplify some calls to getSetCCResultType. NFCBjorn Pettersson2019-07-091-4/+2
* [LegalizeTypes] Fix saturation bug for smul.fix.satBjorn Pettersson2019-07-091-3/+3
* [CodeGen] Add lrint/llrint builtinsAdhemerval Zanella2019-05-281-0/+27
* [Intrinsic] Signed Fixed Point Saturation Multiplication IntrinsicLeonard Chan2019-05-211-8/+134
* [CodeGen] Add lround/llround builtinsAdhemerval Zanella2019-05-161-0/+27
* [SelectionDAG][X86] Use stack load/store in PromoteIntRes_BITCAST when the in...Craig Topper2019-04-251-15/+18
* [SelectionDAG] Handle unary SelectPatternFlavor for ABS case in SelectionDAGB...Simon Pilgrim2019-03-191-0/+26
* [SDAG][AArch64] Legalize VECREDUCENikita Popov2019-03-111-0/+81
* [LegalizeTypes][AArch64][X86] Make type legalization of vector (S/U)ADD/SUB/M...Craig Topper2019-02-241-5/+9
* Recommit r354647 and r354648 "[LegalizeTypes] When promoting the result of EX...Craig Topper2019-02-231-3/+7
* Revert r354363 & co "[X86][SSE] Generalize X86ISD::BLENDI support to more val...Reid Kleckner2019-02-231-7/+3
* [LegalizeTypes] Use PromoteTargetBoolean in PromoteIntOp_ADDSUBCARRY instead ...Craig Topper2019-02-231-13/+1
* [LegalizeTypes] When promoting the result of EXTRACT_SUBVECTOR, also check if...Craig Topper2019-02-221-3/+7
* [SDAG] Use shift amount type in MULO promotion; NFCNikita Popov2019-02-191-2/+4
* [CodeGen] Handle vector UADDO, SADDO, USUBO, SSUBONikita Popov2019-02-071-1/+1
* [Intrinsic] Unsigned Fixed Point Multiplication IntrinsicLeonard Chan2019-02-041-13/+35
* [SelectionDAG] Support promotion of the FPOWI integer operandAlex Bradbury2019-02-011-0/+7
* [SelectionDAG] Codesize: don't expand SHIFT to SHIFT_PARTSSjoerd Meijer2019-01-311-3/+7
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