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authorSimon Pilgrim <llvm-dev@redking.me.uk>2020-01-14 11:20:09 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2020-01-14 11:41:47 +0000
commita43b0065c5c78eba3fb83881fb628f5b8182db64 (patch)
tree983d795963a172cda345f34ac75d1b66d6a29190 /llvm/lib/CodeGen/SelectionDAG
parente73b20c57dc7a8c847ebadeb7e19c08ec84f5bd7 (diff)
downloadbcm5719-llvm-a43b0065c5c78eba3fb83881fb628f5b8182db64.tar.gz
bcm5719-llvm-a43b0065c5c78eba3fb83881fb628f5b8182db64.zip
[SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and generic ISD::SRL handling.
As mentioned by @nikic on rGef5debac4302 (although that was just about SHL), we can merge the guaranteed top zero bits from the shifted value, and then, if a min shift amount is known, zero out the top bits as well. SHL tests / handling will be added in a follow up patch.
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp22
1 files changed, 12 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index a0f621ab50a..64d439f5f78 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2885,23 +2885,25 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
}
break;
case ISD::SRL:
+ Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+
if (const APInt *ShAmt = getValidShiftAmountConstant(Op, DemandedElts)) {
- Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
unsigned Shift = ShAmt->getZExtValue();
Known.Zero.lshrInPlace(Shift);
Known.One.lshrInPlace(Shift);
// High bits are known zero.
Known.Zero.setHighBits(Shift);
- } else if (const APInt *ShMinAmt =
- getValidMinimumShiftAmountConstant(Op, DemandedElts)) {
- // Minimum shift high bits are known zero.
- Known.Zero.setHighBits(ShMinAmt->getZExtValue());
- } else {
- // No matter the shift amount, the leading zeros will stay zero.
- Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
- Known.Zero = APInt::getHighBitsSet(BitWidth, Known.countMinLeadingZeros());
- Known.One.clearAllBits();
+ break;
}
+
+ // No matter the shift amount, the leading zeros will stay zero.
+ Known.Zero = APInt::getHighBitsSet(BitWidth, Known.countMinLeadingZeros());
+ Known.One.clearAllBits();
+
+ // Minimum shift high bits are known zero.
+ if (const APInt *ShMinAmt =
+ getValidMinimumShiftAmountConstant(Op, DemandedElts))
+ Known.Zero.setHighBits(ShMinAmt->getZExtValue());
break;
case ISD::SRA:
if (const APInt *ShAmt = getValidShiftAmountConstant(Op, DemandedElts)) {
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