| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Use uint16_t to store register overlaps to reduce static data. | Craig Topper | 2012-03-04 | 1 | -2/+2 |
| * | PostRA sched: speed up physreg tracking by not abusing SparseSet. | Andrew Trick | 2012-02-24 | 1 | -15/+26 |
| * | misched: cleanup reaching def computation | Andrew Trick | 2012-02-23 | 1 | -3/+5 |
| * | PostRASched: Convert physreg def/use tracking to Jakob's SparseSet. | Andrew Trick | 2012-02-23 | 1 | -78/+86 |
| * | Don't compute latencies for regmask operands. | Jakob Stoklund Olesen | 2012-02-22 | 1 | -1/+3 |
| * | misched: Use SparseSet for VRegDegs for constant time clear(). | Andrew Trick | 2012-02-22 | 1 | -13/+19 |
| * | Comment from code review | Andrew Trick | 2012-02-22 | 1 | -0/+1 |
| * | misched: DAG builder should not track dependencies for SSA defs. | Andrew Trick | 2012-02-22 | 1 | -1/+5 |
| * | Initialize SUnits before DAG building. | Andrew Trick | 2012-02-22 | 1 | -61/+83 |
| * | Clear virtual registers after they are no longer referenced. | Andrew Trick | 2012-02-21 | 1 | -0/+2 |
| * | misched: Initial code for building an MI level scheduling DAG | Andrew Trick | 2012-01-14 | 1 | -8/+86 |
| * | Move physreg dependency generation into aptly named addPhysRegDeps. | Andrew Trick | 2012-01-14 | 1 | -155/+175 |
| * | misched: Added ScheduleDAGInstrs::IsPostRA | Andrew Trick | 2012-01-14 | 1 | -3/+5 |
| * | Added a late machine instruction copy propagation pass. This catches | Evan Cheng | 2012-01-07 | 1 | -6/+1 |
| * | Remove an unused variable. | Chandler Carruth | 2012-01-05 | 1 | -1/+0 |
| * | Minor postra scheduler cleanup. It could result in more precise antidependenc... | Andrew Trick | 2012-01-05 | 1 | -25/+19 |
| * | Model ARM predicated write as read-mod-write. e.g. | Evan Cheng | 2011-12-14 | 1 | -2/+2 |
| * | Allow target to specify register output dependency. Still default to one. | Evan Cheng | 2011-12-14 | 1 | -1/+7 |
| * | - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function | Evan Cheng | 2011-12-14 | 1 | -11/+6 |
| * | Add bundle aware API for querying instruction properties and switch the code | Evan Cheng | 2011-12-07 | 1 | -11/+10 |
| * | First chunk of MachineInstr bundle support. | Evan Cheng | 2011-12-06 | 1 | -1/+1 |
| * | make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instr... | Hal Finkel | 2011-12-02 | 1 | -5/+5 |
| * | PostRA scheduler fix. Clear stale loop dependencies. | Andrew Trick | 2011-10-07 | 1 | -0/+1 |
| * | whitespace | Andrew Trick | 2011-10-07 | 1 | -1/+1 |
| * | Rename TargetSubtarget to TargetSubtargetInfo for consistency. | Evan Cheng | 2011-07-01 | 1 | -2/+2 |
| * | Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries)... | Evan Cheng | 2011-06-29 | 1 | -0/+1 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -16/+16 |
| * | Remove dead code. | Devang Patel | 2011-06-02 | 1 | -8/+3 |
| * | Update DBG_VALUEs while breaking anti dependencies. | Devang Patel | 2011-06-02 | 1 | -1/+1 |
| * | During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALU... | Devang Patel | 2011-06-02 | 1 | -36/+29 |
| * | Added an assertion, and updated a comment. | Andrew Trick | 2011-05-06 | 1 | -5/+8 |
| * | ARM post RA scheduler compile time fix. | Andrew Trick | 2011-05-05 | 1 | -0/+12 |
| * | whitespace | Andrew Trick | 2011-05-05 | 1 | -16/+16 |
| * | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner | 2011-04-15 | 1 | -1/+1 |
| * | Do not model all INLINEASM instructions as having unmodelled side effects. | Evan Cheng | 2011-01-07 | 1 | -1/+1 |
| * | Move Value::getUnderlyingObject to be a standalone | Dan Gohman | 2010-12-15 | 1 | -2/+3 |
| * | Two sets of changes. Sorry they are intermingled. | Evan Cheng | 2010-11-03 | 1 | -3/+5 |
| * | Putting r117193 back except for the compile time cost. Rather than assuming f... | Evan Cheng | 2010-10-27 | 1 | -3/+10 |
| * | Neuter r117193 as it causes significant post-ra scheduler compile time regres... | Evan Cheng | 2010-10-25 | 1 | -2/+2 |
| * | Properly model the latency of register defs which are 1) function returns or | Evan Cheng | 2010-10-23 | 1 | -16/+76 |
| * | Avoid compiler warning: comparison between signed and unsigned integer. | Evan Cheng | 2010-10-08 | 1 | -1/+1 |
| * | Fix operand latency computation in cases where the definition operand is | Evan Cheng | 2010-10-08 | 1 | -0/+11 |
| * | Remove unused variables. | Nick Lewycky | 2010-10-06 | 1 | -3/+0 |
| * | - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This | Evan Cheng | 2010-10-06 | 1 | -5/+4 |
| * | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP | Evan Cheng | 2010-09-29 | 1 | -20/+17 |
| * | Teach if-converter to be more careful with predicating instructions that would | Evan Cheng | 2010-09-10 | 1 | -15/+14 |
| * | Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectors | Bob Wilson | 2010-07-24 | 1 | -1/+2 |
| * | Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. | Bill Wendling | 2010-07-15 | 1 | -3/+3 |
| * | Fix the post-RA instruction scheduler to handle instructions referenced by | Jim Grosbach | 2010-05-19 | 1 | -3/+3 |
| * | Get rid of the EdgeMapping map. Instead, just check for BasicBlock | Dan Gohman | 2010-05-01 | 1 | -2/+1 |
