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| author | Craig Topper <craig.topper@gmail.com> | 2012-03-04 10:43:23 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-03-04 10:43:23 +0000 |
| commit | 1d3265887755f2eac986407343dc7447948e9a72 (patch) | |
| tree | c0af8f45958150e8a5b2f31d2b67a2ac236182ae /llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | |
| parent | dc2cada889b3bcf652fd8f356e2b96cea8e6e228 (diff) | |
| download | bcm5719-llvm-1d3265887755f2eac986407343dc7447948e9a72.tar.gz bcm5719-llvm-1d3265887755f2eac986407343dc7447948e9a72.zip | |
Use uint16_t to store register overlaps to reduce static data.
llvm-svn: 152001
Diffstat (limited to 'llvm/lib/CodeGen/ScheduleDAGInstrs.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index 8f9d85b695b..c0ccdb33e84 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -215,7 +215,7 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned SpecialAddressLatency = ST.getSpecialAddressLatency(); unsigned DataLatency = SU->Latency; - for (const unsigned *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) { + for (const uint16_t *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) { if (!Uses.contains(*Alias)) continue; std::vector<SUnit*> &UseList = Uses[*Alias]; @@ -268,7 +268,7 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { // TODO: Using a latency of 1 here for output dependencies assumes // there's no cost for reusing registers. SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; - for (const unsigned *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) { + for (const uint16_t *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) { if (!Defs.contains(*Alias)) continue; std::vector<SUnit *> &DefList = Defs[*Alias]; |
