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path: root/llvm/lib/CodeGen/PostRASchedulerList.cpp
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* MachineScheduler: Add regpressure information to debug dumpMatthias Braun2015-11-061-2/+6
* ScheduleDAGInstrs: Remove IsPostRA flag; NFCMatthias Braun2015-11-031-1/+1
* CodeGen: Use range-based for in PostRAScheduler, NFCDuncan P. N. Exon Smith2015-10-091-12/+11
* [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatibleChandler Carruth2015-09-091-2/+2
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
* Rename TargetSubtargetInfo::enablePostMachineScheduler() to enablePostRASched...Matthias Braun2015-06-131-1/+1
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-111-1/+1
* The subtarget is cached on the MachineFunction. Access it directly.Eric Christopher2015-01-271-3/+1
* Whitespace.NAKAMURA Takumi2014-10-291-5/+5
* Grab the subtarget and subtarget dependent variables off ofEric Christopher2014-10-141-4/+2
* Cleanup: Delete seemingly unused reference to MachineDominatorTree from Sched...Alexey Samsonov2014-08-201-11/+10
* Fix null reference creation in ScheduleDAGInstrs constructor call.Alexey Samsonov2014-08-201-1/+1
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-1/+1
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-3/+5
* Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel2014-07-151-3/+20
* [Modules] Remove potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check i...Craig Topper2014-04-141-10/+10
* Disable each MachineFunctionPass for 'optnone' functions, unless thatPaul Robinson2014-03-311-0/+3
* remove a bunch of unused private methodsNuno Lopes2014-03-231-1/+0
* [C++11] Add 'override' keyword to virtual methods that override their base cl...Craig Topper2014-03-071-10/+10
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-3/+3
* Move the PostRA scheduler's fixupKills function for reuse.Andrew Trick2013-12-281-160/+3
* Add two additional hazard recognizer functionsHal Finkel2013-12-111-7/+43
* After PostRA scheduling, don't set kill flags on undef operands.Andrew Trick2013-10-161-2/+2
* mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr c...Andrew Trick2013-08-231-7/+18
* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-221-10/+8
* Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen2013-02-051-19/+5
* Use MachineInstrBuilder in a few CodeGen passes.Jakob Stoklund Olesen2012-12-201-5/+3
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-11/+11
* misched: Don't consider artificial edges weak edges.Andrew Trick2012-11-131-1/+1
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-121-7/+7
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-151-3/+2
* Release build: guard dump functions withManman Ren2012-09-111-1/+1
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-061-0/+2
* Add a getName function to MachineFunction. Use it in places that previously d...Craig Topper2012-08-221-1/+1
* Move RegisterClassInfo.h.Andrew Trick2012-06-061-1/+1
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-061-1/+0
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-19/+13
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-231-0/+4
* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...Andrew Trick2012-03-091-7/+7
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-071-1/+1
* misched prep: rename InsertPos to End.Andrew Trick2012-03-071-8/+8
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-071-17/+17
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-071-12/+38
* misched preparation: modularize schedule emission.Andrew Trick2012-03-071-0/+36
* misched preparation: modularize schedule printing.Andrew Trick2012-03-071-0/+18
* misched preparation: modularize schedule verification.Andrew Trick2012-03-071-2/+8
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce stati...Craig Topper2012-03-051-6/+6
* BitVectorize loop.Benjamin Kramer2012-02-231-3/+1
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