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| author | Andrew Trick <atrick@apple.com> | 2012-03-07 05:21:36 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-03-07 05:21:36 +0000 |
| commit | 46a58664f7c9a4a15988074fd5d6ae11992b4b21 (patch) | |
| tree | b0119d1bc47ee4042210e14f1b98c162e48f3aea /llvm/lib/CodeGen/PostRASchedulerList.cpp | |
| parent | 7c6c41a56ab0885c96f30444df73014c92ecb625 (diff) | |
| download | bcm5719-llvm-46a58664f7c9a4a15988074fd5d6ae11992b4b21.tar.gz bcm5719-llvm-46a58664f7c9a4a15988074fd5d6ae11992b4b21.zip | |
misched preparation: modularize schedule verification.
ScheduleDAG will not refer to the scheduled instruction sequence.
llvm-svn: 152204
Diffstat (limited to 'llvm/lib/CodeGen/PostRASchedulerList.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/PostRASchedulerList.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index e59aa9d51b0..4c768acb54f 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -703,6 +703,12 @@ void SchedulePostRATDList::ListScheduleTopDown() { } #ifndef NDEBUG - VerifySchedule(/*isBottomUp=*/false); -#endif + unsigned ScheduledNodes = VerifyScheduledDAG(/*isBottomUp=*/false); + unsigned Noops = 0; + for (unsigned i = 0, e = Sequence.size(); i != e; ++i) + if (!Sequence[i]) + ++Noops; + assert(Sequence.size() - Noops == ScheduledNodes && + "The number of nodes scheduled doesn't match the expected number!"); +#endif // NDEBUG } |
