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* Let MachineVerifier be aware of mem-to-mem instructions.Jonas Paulsson2015-10-211-2/+8
| | | | | | | | | | | | | | | A mem-to-mem instruction (that both loads and stores), which store to an FI, cannot pass the verifier since it thinks it is loading from the FI. For the mem-to-mem instruction, do a looser check in visitMachineOperand() and only check liveness at the reg-slot while analyzing a frame index operand. Needed to make CodeGen/SystemZ/xor-01.ll pass with -verify-machineinstrs, which now runs with this flag. Reviewed by Evan Cheng and Quentin Colombet. llvm-svn: 250885
* CodeGen: Continue removing ilist iterator implicit conversionsDuncan P. N. Exon Smith2015-10-091-20/+25
| | | | llvm-svn: 249884
* TargetRegisterInfo: Introduce PrintLaneMask.Matthias Braun2015-09-251-3/+2
| | | | | | | This makes it more convenient to print lane masks and lead to more uniform printing. llvm-svn: 248624
* TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where ↵Matthias Braun2015-09-251-10/+11
| | | | | | apropriate; NFC llvm-svn: 248623
* Save LaneMask with livein registersMatthias Braun2015-09-091-5/+5
| | | | | | | | | | | | | | | | | With subregister liveness enabled we can detect the case where only parts of a register are live in, this is expressed as a 32bit lanemask. The current code only keeps registers in the live-in list and therefore enumerated all subregisters affected by the lanemask. This turned out to be too conservative as the subregister may also cover additional parts of the lanemask which are not live. Expressing a given lanemask by enumerating a minimum set of subregisters is computationally expensive so the best solution is to simply change the live-in list to store the lanemasks as well. This will reduce memory usage for targets using subregister liveness and slightly increase it for other targets Differential Revision: http://reviews.llvm.org/D12442 llvm-svn: 247171
* MachineVerifier: Check that SlotIndex MBBIndexList is sorted.Matthias Braun2015-09-091-0/+17
| | | | | | | This introduces a check that the MBBIndexList is sorted as proposed in http://reviews.llvm.org/D12443 but split up into a separate commit. llvm-svn: 247166
* [WinEH] Add some support for code generating catchpadReid Kleckner2015-08-271-3/+3
| | | | | | | We can now run 32-bit programs with empty catch bodies. The next step is to change PEI so that we get funclet prologues and epilogues. llvm-svn: 246235
* MachineBasicBlock: Add liveins() method returning an iterator_rangeMatthias Braun2015-08-241-9/+5
| | | | llvm-svn: 245895
* MachineVerifier: Handle the optional def operand in a PATCHPOINT instruction.Alex Lorenz2015-08-101-1/+4
| | | | | | | | | | | | The PATCHPOINT instructions have a single optional defined register operand, but the machine verifier can't verify the optional defined register operands. This commit makes sure that the machine verifier won't report an error when a PATCHPOINT instruction doesn't have its optional defined register operand. This change will allow us to enable the machine verifier for the code generation tests for the patchpoint intrinsics. Reviewers: Juergen Ributzka llvm-svn: 244513
* LiveInterval: Document and enforce rules about empty subranges.Matthias Braun2015-07-161-0/+2
| | | | | | | | | Empty subranges are not allowed in a LiveInterval and must be removed instead: Check this in the verifiers, put a reminder for this in the comment of the shrinkToUses variant for a single lane and make it automatic for the shrinkToUses variant for a LiveInterval. llvm-svn: 242431
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-2/+2
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-2/+2
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* MachineFrameInfo: Simplify pristine register calculation.Matthias Braun2015-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | About pristine regsiters: Pristine registers "hold a value that is useless to the current function, but that must be preserved - they are callee saved registers that have not been saved." This concept saves compile time as it frees the prologue/epilogue inserter from adding every such register to every basic blocks live-in list. However the current code in getPristineRegs is formulated in a complicated way: Inside the function prologue and epilogue all callee saves are considered pristine, while in the rest of the code only the non-saved ones are considered pristine. This requires logic to differentiate between prologue/epilogue and the rest and in the presence of shrink-wrapping this even becomes complicated/expensive. It's also unnecessary because the prologue epilogue inserters already mark callee-save registers that are saved/restores properly in the respective blocks in the prologue/epilogue (see updateLiveness() in PrologueEpilogueInserter.cpp). So only declaring non-saved/restored callee saved registers as pristine just works. Differential Revision: http://reviews.llvm.org/D10101 llvm-svn: 238524
* MachineInstr: Change return value of getOpcode() to unsigned.Matthias Braun2015-05-181-2/+2
| | | | | | | | | This was previously returning int. However there are no negative opcode numbers and more importantly this was needlessly different from MCInstrDesc::getOpcode() (which even is the value returned here) and SDValue::getOpcode()/SDNode::getOpcode(). llvm-svn: 237611
* Fix typoMatt Arsenault2015-04-301-1/+1
| | | | llvm-svn: 236283
* MachineVerifier: Don't crash if MachineOperand has no parentMatt Arsenault2015-04-301-2/+12
| | | | | | | | If you somehow added a MachineOperand to an instruction that did not have the parent set, the verifier would crash since it attempts to use the operand's parent. llvm-svn: 236249
* MachineVerifier: slightly simplify code that is only called with vregsMatthias Braun2015-03-251-30/+25
| | | | llvm-svn: 233216
* Do not track subregister liveness when it brings no benefitsMatthias Braun2015-03-191-1/+2
| | | | | | | | | | | Some subregisters are only to indicate different access sizes, while not providing any way to actually divide the register up into multiple disjunct parts. Avoid tracking subregister liveness in these cases as it is not beneficial. Differential Revision: http://reviews.llvm.org/D8429 llvm-svn: 232695
* [llvm] Replacing asserts with static_asserts where appropriateGabor Horvath2015-03-161-1/+1
| | | | | | | | | | | | | | | | Summary: This patch consists of the suggestions of clang-tidy/misc-static-assert check. Reviewers: alexfh Reviewed By: alexfh Subscribers: xazax.hun, llvm-commits Differential Revision: http://reviews.llvm.org/D8343 llvm-svn: 232366
* Have TargetRegisterInfo::getLargestLegalSuperClass take aEric Christopher2015-03-101-1/+1
| | | | | | | MachineFunction argument so that it can look up the subtarget rather than using a cached one in some Targets. llvm-svn: 231888
* Rewrite MachineOperand::print and MachineInstr::print to avoidEric Christopher2015-02-271-1/+1
| | | | | | | | | | | | uses of TM->getSubtargetImpl and propagate to all calls. This could be a debugging regression in places where we had a TargetMachine and/or MachineFunction but don't have it as part of the MachineInstr. Fixing this would require passing a MachineFunction/Function down through the print operator, but none of the existing uses in tree seem to do this. llvm-svn: 230710
* Remove a gross usage of environment variables in MachineVerifier, replacing ↵Owen Anderson2015-02-041-95/+74
| | | | | | | | it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
* MachineVerifier: Allow undef reads if a matching superreg is defined.Matthias Braun2015-01-141-0/+19
| | | | | | | | | | | | | | | | | | | Summary: Some pseudo instruction expansions break down a wide register use into multiple uses of smaller sub registers. If the super register was partially undefined the broken down sub registers may be completely undefined now leading to MachineVerifier complaints. Unfortunately liveness information to add the required dead flags is not easily (cheaply) available when expanding pseudo instructions. This commit changes the verifier to be quiet if there is an additional implicit use of a super register. Pseudo instruction expanders can use this to mark cases where partially defined values get potentially broken into completely undefined ones. Differential Revision: http://reviews.llvm.org/D6973 llvm-svn: 226047
* [CodeGen] Let MachineVerifierPass own its banner stringMatthias Braun2014-12-111-5/+5
| | | | llvm-svn: 224041
* LiveInterval: Use range based for loops for subregister ranges.Matthias Braun2014-12-111-7/+6
| | | | llvm-svn: 223991
* LiveInterval: Use more range based for loops for value numbers and segments.Matthias Braun2014-12-101-3/+2
| | | | llvm-svn: 223978
* MachineVerifier: Allow physreg use if just a subreg is defined.Matthias Braun2014-12-101-1/+12
| | | | | | | | We can't mark partially undefined registers, so we have to allow reading a register in the machine verifier if just parts of a register are defined. llvm-svn: 223896
* MachineVerifier: Allow LiveInterval segments to end at a partial write.Matthias Braun2014-12-101-2/+10
| | | | | | | | In the subregister liveness tracking case we do not create implicit reads on partial register writes anymore, still we need to produce a new SSA value for partial writes so the live segment has to end. llvm-svn: 223895
* LiveInterval: Add support to track liveness of subregisters.Matthias Braun2014-12-101-31/+74
| | | | | | This code adds the required data structures. Algorithms to compute it follow. llvm-svn: 223877
* [MachineVerifier] Accept a MBB with a single landing pad successor.Ahmed Bougacha2014-12-011-1/+5
| | | | | | | | | | | | | | | The MachineVerifier used to check that there was always exactly one unconditional branch to a non-landingpad (normal) successor. If that normal successor to an invoke BB is unreachable, it seems reasonable to only have one successor, the landing pad. On targets other than AArch64 (and on AArch64 with a different testcase), the branch folder turns the branch to the landing pad into a fallthrough. The MachineVerifier, which relies on AnalyzeBranch, is unable to check the condition, and doesn't complain. However, it does in this specific testcase, where the branch to the landing pad remained. Make the MachineVerifier accept it. llvm-svn: 223059
* MachineVerifier: Report register for bad liverangesMatthias Braun2014-11-191-24/+28
| | | | llvm-svn: 222380
* Move register class name strings to a single array in MCRegisterInfo to ↵Craig Topper2014-11-171-5/+6
| | | | | | | | reduce static table size and number of relocation entries. Indices into the table are stored in each MCRegisterClass instead of a pointer. A new method, getRegClassName, is added to MCRegisterInfo and TargetRegisterInfo to lookup the string in the table. llvm-svn: 222118
* Access subtarget specific variables off of the MachineFunction'sEric Christopher2014-10-141-2/+2
| | | | | | cached subtarget and not the TargetMachine. llvm-svn: 219668
* Modernize raw_fd_ostream's constructor a bit.Rafael Espindola2014-08-251-4/+5
| | | | | | | | | | Take a StringRef instead of a "const char *". Take a "std::error_code &" instead of a "std::string &" for error. A create static method would be even better, but this patch is already a bit too big. llvm-svn: 216393
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-2/+3
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* MachineVerifier: Clean up some syntactic weirdness left behind by find&replace.Benjamin Kramer2014-05-241-6/+6
| | | | | | No functionality change. llvm-svn: 209581
* CodeGen: Make MachineBasicBlock::back skip to the beginning of the last bundle.Benjamin Kramer2014-05-241-9/+8
| | | | | | | | | | | | This makes front/back symmetric with begin/end, avoiding some confusion. Added instr_front/instr_back for the old behavior, corresponding to instr_begin/instr_end. Audited all three in-tree users of back(), all of them look like they don't want to look inside bundles. Fixes an assertion (PR19815) when generating debug info on mips, where a delay slot was bundled at the end of a branch. llvm-svn: 209580
* Convert more loops to range-based equivalentsAlexey Samsonov2014-04-301-16/+16
| | | | llvm-svn: 207714
* Convert several loops over MachineFunction basic blocks to range-based loopsAlexey Samsonov2014-04-301-33/+25
| | | | llvm-svn: 207683
* raw_ostream: Forward declare OpenFlags and include FileSystem.h only where ↵Benjamin Kramer2014-04-291-0/+1
| | | | | | necessary. llvm-svn: 207593
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-141-9/+9
| | | | | | instead of comparing to nullptr. llvm-svn: 206142
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-071-2/+2
| | | | | | class. llvm-svn: 203220
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-1/+1
| | | | | | Remove the old functions. llvm-svn: 202636
* Replace the F_Binary flag with a F_Text one.Rafael Espindola2014-02-241-1/+2
| | | | | | | | | After this I will set the default back to F_None. The advantage is that before this patch forgetting to set F_Binary would corrupt a file on windows. Forgetting to set F_Text produces one that cannot be read in notepad, which is a better failure mode :-) llvm-svn: 202052
* Fix confusing machine verifier error.Matt Arsenault2013-11-151-1/+1
| | | | | | | | | | | The error reported the number of explicit operands, but that isn't what is checked. In my case, this resulted in the confusing errors "Too few operands." followed shortly by "8 operands expected, but 8 given." llvm-svn: 194862
* increase the accuracy of register pressure computation in the presence of ↵Pedro Artigas2013-11-081-10/+9
| | | | | | dead definitions by using live intervals, if available, to identify dead definitions and proceed accordingly. llvm-svn: 194286
* Print register in LiveInterval::print()Matthias Braun2013-10-101-12/+2
| | | | llvm-svn: 192398
* Represent RegUnit liveness with LiveRange instanceMatthias Braun2013-10-101-6/+6
| | | | | | | Previously LiveInterval has been used, but having a spill weight and register number is unnecessary for a register unit. llvm-svn: 192397
* Change MachineVerifier to work on LiveRange + LiveIntervalMatthias Braun2013-10-101-92/+117
| | | | llvm-svn: 192395
* Pass LiveQueryResult by valueMatthias Braun2013-10-101-2/+2
| | | | | | | This makes the API a bit more natural to use and makes it easier to make LiveRanges implementation details private. llvm-svn: 192394
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