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* misched: Use the same scheduling heuristics with -misched-topdown/bottomup.Andrew Trick2012-05-241-2/+16
| | | | | | (except the part about choosing direction) llvm-svn: 157437
* misched: Trace regpressure.Andrew Trick2012-05-241-2/+4
| | | | llvm-svn: 157429
* misched: Give each ReadyQ a unique IDAndrew Trick2012-05-241-36/+45
| | | | llvm-svn: 157428
* misched: Added ScoreboardHazardRecognizer.Andrew Trick2012-05-241-49/+232
| | | | | | | | | | | | | | | | | | | The Hazard checker implements in-order contraints, or interlocked resources. Ready instructions with hazards do not enter the available queue and are not visible to other heuristics. The major code change is the addition of SchedBoundary to encapsulate the state at the top or bottom of the schedule, including both a pending and available queue. The scheduler now counts cycles in sync with the hazard checker. These are minimum cycle counts based on known hazards. Targets with no itinerary (x86_64) currently remain at cycle 0. To fix this, we need to provide some maximum issue width for all targets. We also need to add the concept of expected latency vs. minimum latency. llvm-svn: 157427
* misched: Release bottom roots in reverse order.Andrew Trick2012-05-241-9/+23
| | | | llvm-svn: 157426
* misched: rename ReadyQ classAndrew Trick2012-05-241-8/+9
| | | | llvm-svn: 157425
* misched: copy comments so compareRPDelta is readable by itself.Andrew Trick2012-05-241-1/+4
| | | | llvm-svn: 157424
* commentsAndrew Trick2012-05-171-2/+3
| | | | llvm-svn: 157020
* misched: trace ReadyQ.Andrew Trick2012-05-171-0/+8
| | | | llvm-svn: 157007
* misched: Added 3-level regpressure back-off.Andrew Trick2012-05-171-36/+184
| | | | | | | | | | | | | | | | | | Introduce the basic strategy for register pressure scheduling. 1) Respect target limits at all times. 2) Indentify critical register classes (pressure sets). Track pressure within the scheduled region. Avoid increasing scheduled pressure for critical registers. 3) Avoid exceeding the max pressure of the region prior to scheduling. Added logic for picking between the top and bottom ready Q's based on regpressure heuristics. Status: functional but needs to be asjusted to achieve good results. llvm-svn: 157006
* commentAndrew Trick2012-05-171-2/+0
| | | | llvm-svn: 157005
* misched: fix liveness iteratorsAndrew Trick2012-05-171-10/+16
| | | | llvm-svn: 157003
* misched: Print machineinstrs with -debug-only=mischedAndrew Trick2012-05-101-0/+2
| | | | llvm-svn: 156576
* misched: tracing register pressure heuristics.Andrew Trick2012-05-101-6/+22
| | | | llvm-svn: 156575
* misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick2012-05-101-38/+144
| | | | | | | | | | | Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. llvm-svn: 156574
* misched: Release only unscheduled nodes into ReadyQ.Andrew Trick2012-05-101-2/+8
| | | | llvm-svn: 156573
* misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick2012-05-101-11/+44
| | | | llvm-svn: 156572
* misched: Introducing Top and Bottom register pressure trackers during ↵Andrew Trick2012-05-101-10/+71
| | | | | | scheduling. llvm-svn: 156571
* Fix a naughty header include that breaks "installed" builds.Andrew Trick2012-04-241-2/+12
| | | | llvm-svn: 155486
* misched: try (not too hard) to place debug values where they belongAndrew Trick2012-04-241-0/+25
| | | | llvm-svn: 155458
* misched: ignore debug values during schedulingAndrew Trick2012-04-241-6/+31
| | | | llvm-svn: 155457
* misched: DAG builder support for tracking register pressure within the ↵Andrew Trick2012-04-241-4/+48
| | | | | | | | | current scheduling region. The DAG builder is a convenient place to do it. Hopefully this is more efficient than a separate traversal over the same region. llvm-svn: 155456
* misched: Add finalizeScheduler to complete the target interface.Andrew Trick2012-04-011-0/+1
| | | | llvm-svn: 153827
* misched: trace LiveIntervals after scheduling.Andrew Trick2012-03-211-0/+1
| | | | llvm-svn: 153161
* misched: obvious iterator update fixes for bottom-up.Andrew Trick2012-03-211-0/+6
| | | | llvm-svn: 153160
* misched: cleanup main loopAndrew Trick2012-03-211-10/+14
| | | | llvm-svn: 153159
* Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames2012-03-191-1/+19
| | | | | | | instructions have been scheduled. Handy for tracking down scheduler bugs, or bugs exposed by scheduling. llvm-svn: 153045
* Silence operator precedence warnings.Benjamin Kramer2012-03-141-3/+3
| | | | llvm-svn: 152711
* misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick2012-03-141-98/+266
| | | | | | | | | | | | | | | | | | | New flags: -misched-topdown, -misched-bottomup. They can be used with the default scheduler or with -misched=shuffle. Without either topdown/bottomup flag -misched=shuffle now alternates scheduling direction. LiveIntervals update is unimplemented with bottom-up scheduling, so only -misched-topdown currently works. Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class. ScheduleDAGMI is aware of the top and bottom of the unscheduled zone within the current region. Scheduling policy can be plugged into the ScheduleDAGMI driver by implementing MachineSchedStrategy. ConvergingScheduler is now the default scheduling algorithm. It exercises the new driver but still does no reordering. llvm-svn: 152700
* misched commentsAndrew Trick2012-03-141-0/+15
| | | | llvm-svn: 152699
* misched: handle scheduler that insert instructions at empty region boundaries.Andrew Trick2012-03-091-3/+12
| | | | | | And add comments, since this is obviously confusing. llvm-svn: 152445
* misched: handle scheduling region boundaries nicely.Andrew Trick2012-03-091-4/+11
| | | | llvm-svn: 152393
* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are ↵Andrew Trick2012-03-091-3/+3
| | | | | | not private. llvm-svn: 152382
* misched commentsAndrew Trick2012-03-091-2/+3
| | | | llvm-svn: 152374
* revert 152356: verify misched changes using -misched=shuffle.Andrew Trick2012-03-091-3/+3
| | | | llvm-svn: 152373
* misched: allow the default scheduler to be one chosen by the target.Andrew Trick2012-03-091-16/+33
| | | | llvm-svn: 152360
* Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().Evan Cheng2012-03-091-3/+3
| | | | llvm-svn: 152356
* misched interface: Expose the MachineScheduler pass.Andrew Trick2012-03-081-144/+102
| | | | | | | | Allow targets to provide their own schedulers (subclass of ScheduleDAGInstrs) to the misched pass. Select schedulers using -misched=... llvm-svn: 152278
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-071-1/+1
| | | | | | implement their own MachineScheduler. llvm-svn: 152261
* misched prep: rename InsertPos to End.Andrew Trick2012-03-071-1/+1
| | | | | | ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted. llvm-svn: 152256
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-071-12/+12
| | | | | | | We had half the API with one convention, half with another. Now was a good time to clean it up. llvm-svn: 152255
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-071-10/+16
| | | | | | | | | | | | | | | | | | | ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. llvm-svn: 152208
* Added -view-misched=dags options.Andrew Trick2012-03-071-0/+9
| | | | llvm-svn: 152178
* misched: Use the StartBlock/FinishBlock hooksAndrew Trick2012-03-071-0/+2
| | | | llvm-svn: 152172
* Initialize SUnits before DAG building.Andrew Trick2012-02-221-6/+7
| | | | | | | | | | | | Affect on SD scheduling and postRA scheduling: Printing the DAG will display the nodes in top-down topological order. This matches the order within the MBB and makes my life much easier in general. Affect on misched: We don't need to track virtual register uses at all. This is awesome. I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A. llvm-svn: 151135
* MachineScheduler shouldn't use/preserve LiveDebugVariables.Lang Hames2012-02-171-4/+0
| | | | llvm-svn: 150773
* Disentangle moving a machine instr from updating LiveIntervals.Lang Hames2012-02-151-1/+2
| | | | llvm-svn: 150552
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-101-8/+0
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226
* commentAndrew Trick2012-02-091-1/+1
| | | | llvm-svn: 150121
* misched: bug in debug output.Andrew Trick2012-02-081-2/+4
| | | | llvm-svn: 150043
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