summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/MachineRegisterInfo.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.Jakob Stoklund Olesen2010-10-061-0/+14
| | | | | | | | This function is intended to be used when inserting a machine instruction that trivially restricts the legal registers, like LEA requiring a GR32_NOSP argument. llvm-svn: 115875
* Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.Jakob Stoklund Olesen2010-07-101-6/+3
| | | | llvm-svn: 108062
* Teach EmitLiveInCopies to omit copies for unused virtual registers,Dan Gohman2010-06-241-14/+25
| | | | | | and to clean up unused incoming physregs from the live-in list. llvm-svn: 106805
* Don't leak RegClass2VRegMap, which is now a new[] array instead of aDan Gohman2010-06-181-0/+1
| | | | | | std::vector. llvm-svn: 106298
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-181-2/+2
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* Remove unused function.Benjamin Kramer2010-05-291-69/+0
| | | | llvm-svn: 105100
* Remove schedule-livein-copies. It's not being used.Evan Cheng2010-05-291-30/+12
| | | | llvm-svn: 105095
* Avoid adding duplicate function live-in's.Evan Cheng2010-05-241-0/+9
| | | | llvm-svn: 104560
* Add a utility function for conservatively clearing kill flags, and makeDan Gohman2010-05-131-0/+9
| | | | | | use of it in MachineCSE. llvm-svn: 103726
* Silence warningJakob Stoklund Olesen2010-05-111-1/+1
| | | | llvm-svn: 103508
* Simplify the tracking of used physregs to a bulk bitor followed by a transitiveJakob Stoklund Olesen2010-05-111-0/+9
| | | | | | | | closure after allocating all blocks. Add a few more test cases for -regalloc=fast. llvm-svn: 103500
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-2/+4
| | | | | | doesn't have to guess. llvm-svn: 103194
* Replace r102368 with code that's less fragile. This creates DBG_VALUE ↵Evan Cheng2010-04-281-28/+9
| | | | | | instructions for function arguments early and insert them after instruction selection is done. llvm-svn: 102554
* Insert dbg_value instructions for function entry block liveins (i.e. ↵Evan Cheng2010-04-261-1/+30
| | | | | | function arguments). llvm-svn: 102368
* Move the code for initialing the entry block livein set out ofDan Gohman2010-04-141-0/+5
| | | | | | SelectionDAGISel. llvm-svn: 101258
* Move the code for emitting livein copies out of SelectionDAGISel.Dan Gohman2010-04-141-0/+106
| | | | llvm-svn: 101254
* Move MachineRegisterInfo's isLiveIn and isLiveOut out of line.Dan Gohman2010-04-131-0/+14
| | | | llvm-svn: 101145
* Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.Evan Cheng2010-03-031-0/+13
| | | | llvm-svn: 97663
* Simplify a few more uses of reg_iterator.Dan Gohman2009-09-251-5/+3
| | | | llvm-svn: 82812
* Part 1.Evan Cheng2009-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng2009-06-141-0/+2
| | | | | | MachineRegisterInfo. This allows more passes to set them. llvm-svn: 73346
* Move MachineRegisterInfo::setRegClass out of line.Dan Gohman2009-04-151-0/+20
| | | | llvm-svn: 69126
* Move createVirtualRegister out-of-line.Dan Gohman2008-12-081-0/+18
| | | | llvm-svn: 60684
* Add a register class -> virtual registers map.Evan Cheng2008-10-201-0/+1
| | | | llvm-svn: 57844
* Assert that all MachineInstrs update PhysRegUseDefLists inDan Gohman2008-07-071-0/+3
| | | | | | their cleanup code. llvm-svn: 53194
* Added debugging routine dumpUses.Evan Cheng2008-02-131-0/+8
| | | | llvm-svn: 47042
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-5/+5
| | | | llvm-svn: 46930
* switch the register iterator to act more like hte LLVM value iterator: ↵Chris Lattner2008-01-011-2/+16
| | | | | | | | | | | dereferencing it now returns the machineinstr of the use. To get the operand, use I.getOperand(). Add a new MachineRegisterInfo::replaceRegWith, which is basically like Value::replaceAllUsesWith. llvm-svn: 45482
* Add a trivial but handy function to efficiently return the machine Chris Lattner2008-01-011-0/+15
| | | | | | instruction that defines the specified vreg. Crazy. llvm-svn: 45480
* Implement automatically updated def/use lists for all MachineInstr register Chris Lattner2008-01-011-1/+27
| | | | | | | operands. The lists are currently kept in MachineRegisterInfo, but it does not yet provide an iterator interface to them. llvm-svn: 45477
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-0/+20
that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
OpenPOWER on IntegriCloud