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path: root/llvm/lib/CodeGen/MIRParser/MIParser.cpp
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* [MIRParser] Allow generic register specification on operand.Ahmed Bougacha2017-01-201-12/+16
* MIRParser: Allow regclass specification on operandMatthias Braun2017-01-181-2/+69
* [GlobalISel] More fix for the size vs. type typo. NFC.Quentin Colombet2016-12-221-3/+3
* [MIRParser] Fix a typo in comment and error message.Quentin Colombet2016-12-221-2/+2
* [MIRParser] Non-generic virtual register may have a type.Quentin Colombet2016-12-221-3/+0
* [MIRParser] Add parsing hex literals of arbitrary size as unsigned integersKrzysztof Parzyszek2016-12-161-13/+38
* Extract LaneBitmask into a separate typeKrzysztof Parzyszek2016-12-151-3/+6
* Move FrameInstructions from MachineModuleInfo to MachineFunctionMatthias Braun2016-11-301-7/+5
* [MIRPrinter] Print raw branch probabilities as expected by MIRParserGeoff Berry2016-11-181-1/+2
* MIRParser: Add support for parsing vreg reg alloc hintsTom Stellard2016-11-151-0/+23
* Fix Clang-tidy readability-redundant-string-cstr warningsMalcolm Parsons2016-11-021-1/+1
* [MIRParser] Parse lane masks for register live-insKrzysztof Parzyszek2016-10-121-9/+39
* MIRParser: allow types on registers with a RegBank.Tim Northover2016-10-111-1/+2
* MIRParser: generic register operands with typesMatthias Braun2016-10-111-1/+1
* MIRParser: Rewrite register info initialization; mostly NFCMatthias Braun2016-10-111-43/+65
* [MIRParser] Delete dead code. NFCI.Davide Italiano2016-09-211-12/+0
* Don't create a SymbolTable in Function when the LLVMContext discards value na...Mehdi Amini2016-09-171-3/+3
* GlobalISel: remove "unsized" LLTTim Northover2016-09-151-5/+1
* GlobalISel: cache pointer sizes in LLTTim Northover2016-09-151-1/+3
* GlobalISel: disambiguate types when printing MIRTim Northover2016-09-121-6/+21
* [CodeGen] Split out the notions of MI invariance and MI dereferenceability.Justin Lebar2016-09-111-0/+3
* GlobalISel: move type information to MachineRegisterInfo.Tim Northover2016-09-091-26/+6
* [MC] Move .cv_loc management logic out of MCContextReid Kleckner2016-08-261-0/+1
* GlobalISel: legalize integer comparisons on AArch64.Tim Northover2016-08-231-1/+1
* GlobalISel: support irtranslation of icmp instructions.Tim Northover2016-08-171-0/+62
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-1/+1
* CodeGen: add new "intrinsic" MachineOperand kind.Tim Northover2016-07-291-0/+34
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-1/+1
* [MIRParser] Accept unsized generic instructions.Ahmed Bougacha2016-07-281-6/+2
* MIRParser: Use dot instead of colon to mark subregistersMatthias Braun2016-07-261-3/+3
* GlobalISel: omit braces on MachineInstr types when there's only one.Tim Northover2016-07-261-4/+10
* GlobalISel: allow multiple types on MachineInstrs.Tim Northover2016-07-221-7/+14
* GlobalISel: implement alloca instructionTim Northover2016-07-221-2/+8
* GlobalISel: implement low-level type with just size & vector lanes.Tim Northover2016-07-201-35/+42
* [GlobalISel] Mark newly-created gvregs as having a bank.Ahmed Bougacha2016-07-191-1/+5
* MIParser: reject subregister indexes on physregsMatthias Braun2016-07-161-0/+2
* [CodeGen] Take a MachineMemOperand::Flags in MachineFunction::getMachineMemOp...Justin Lebar2016-07-151-4/+4
* MIRParser: Move SlotMapping and SourceMgr refs to PFS; NFCMatthias Braun2016-07-131-52/+29
* MIRParser: Move MachineFunction reference into PFS; NFCMatthias Braun2016-07-131-33/+34
* [MIR] Check that generic virtual registers get a size.Quentin Colombet2016-06-081-4/+6
* MIR: Fix parsing of stack object references in MachineMemOperandsMatthias Braun2016-06-081-1/+10
* MIR: Support MachineMemOperands without associated valueMatthias Braun2016-06-041-7/+9
* MIRParser: Add %subreg.xxx syntax for subregister index operandsMatthias Braun2016-03-281-0/+14
* [MIR] Teach the parser how to parse complex types of generic machine instruct...Quentin Colombet2016-03-081-14/+29
* [MIR] Teach the mir parser about types on generic machine instructions.Quentin Colombet2016-03-081-0/+33
* [MIR] Teach the parser how to handle the size of generic virtual registers.Quentin Colombet2016-03-071-8/+36
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical...Craig Topper2015-12-051-2/+2
* Replace all weight-based interfaces in MBB with probability-based interfaces,...Cong Hou2015-12-011-1/+2
* Revert r254348: "Replace all weight-based interfaces in MBB with probability-...Hans Wennborg2015-12-011-2/+1
* Replace all weight-based interfaces in MBB with probability-based interfaces,...Cong Hou2015-12-011-1/+2
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